Hardware Board Validation Engineering, Director

Astera Labs; San Jose (CA); On-site; USD 239,000 - 265,000; Full time

Job summary

Astera Labs is seeking a Director of Hardware Board Validation Engineering to lead the development, bring-up, and validation of board products for rack-scale AI infrastructure. You will guide projects from concept through production, collaborating with ASIC, firmware, systems, and manufacturing teams to ensure reliable, high-performance hardware.

This hands-on leadership role requires strong technical leadership, excellent communication, and the ability to drive validation programs in a

Qualifications

• BS in Electrical Engineering; MS preferred.
• 12–15+ years at Director level.
• Technical management of hardware design, validation, or system engineering teams.
• Experience with system-level board design from component selection to production release.
• Strong background in high-speed board design for data center/server/networking/AI infrastructure.

Responsibilities

• Lead board validation strategy across definition, architecture, bring-up, test, and production release.
• Direct board bring-up, silicon/PCB debug, system characterization, margin analysis, and performance optimization.
• Collaborate with ASIC, firmware, mechanical, thermal, quality, and manufacturing teams to deliver robust board products.
• Build and mentor a high-performing hardware engineering team and drive mass production readiness.

Skills

Technical leadership

Cross-functional collaboration

Problem-solving

Technical communication

Education

Bachelor’s degree in Electrical Engineering

Master’s degree preferred

Tools

Cadence

Altium

Cadence Allegro

Job description

Hardware Board Validation Engineering, Director

San Jose, California, United States

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Director, Hardware Board Validation Engineering

On-Site - San Jose, Ca

Role Overview

Astera Labs is seeking a Director of Hardware Board Validation Engineering to lead the development, bring-up, and validation of board products that enable rack-scale AI infrastructure. Working closely with ASIC, systems, firmware, signal integrity, power integrity, mechanical, thermal, manufacturing, and customer engineering teams, you will guide products from concept and architecture through qualification and mass production.

This is a hands-on leadership role in a fast-moving environment. You will lead a talented engineering team while stepping in to solve complex technical problems, engage directly with customers, and improve hardware development processes. Your work will help ensure Astera Labs’ connectivity and memory products deliver reliable, high-performance systems for cloud service providers, server manufacturers, and networking OEMs.

Key Responsibilities

• Board Product Strategy and Technical Leadership
  • Lead board validation strategy across product definition, architecture, component selection, schematic capture, layout review, bring-up, debug, optimization, qualification, and production release.
  • Define validation plans, coverage goals, risk assessments, schedules, and exit criteria for high-speed boards, add-in cards, modules, and system platforms.
  • Make hands-on technical contributions to unblock critical design, validation, and customer issues in a dynamic, fast-paced environment.
• High-Speed Hardware Validation
  • Direct board bring-up, silicon/PCB debug, system characterization, margin analysis, and performance optimization across voltage, temperature, channel, and workload conditions.
  • Validate high-speed NRZ and PAM4 SerDes-based protocols, including PCIe Gen 3 and above and Ethernet 25G and above, as well as LPDDR4/5 or related memory interfaces.
  • Apply signal integrity, power integrity, and power architecture expertise to identify risks and drive practical solutions across circuits, power distribution, connectors, sockets, and cables.
• Cross-Functional and Customer Execution
  • Partner with ASIC, post-silicon validation, firmware, systems, mechanical, thermal, quality, compliance, manufacturing, and customer engineering teams to deliver robust board products.
  • Engage key customers to understand system requirements, evaluate form factors, propose complete board solutions, and resolve issues through production support.
  • Collaborate with contract manufacturers, PCB vendors, and external suppliers to ensure designs are manufacturable, testable, and scalable.
• Team Development and Productization
  • Build, mentor, and develop a high-performing hardware engineering team while establishing clear ownership, technical standards, and execution mechanisms.
  • Drive products from concept to mass production, including design reviews, validation reporting, manufacturing readiness, documentation, and post-production support.
  • Improve hardware development methodologies, lessons learned, and reusable validation practices across Astera Labs’ connectivity and memory product portfolio.

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field. Master’s degree in Electrical Engineering preferred.
• 12 - 15+ years of relevant experience, consistent with Astera Labs’ standardized Director level.
• Technical management experience leading hardware design, validation, or system engineering teams.
• Experience with system-level board design from component selection and schematic capture through board bring-up, debug, optimization, validation, and production release.
• Strong background in high-speed board design for enterprise, data center, server, storage, networking, or AI infrastructure systems.
• Strong cross-functional collaboration, technical communication, prioritization, and independent problem-solving skills.

Preferred Qualifications.

• Experience with PCIe add-in cards, CEM cards, paddle cards, active electrical cables, servers, JBOD/JBOG systems, networking switches or routers, interconnects, or optical platforms.
• Proficiency with schematic capture and PCB layout tools such as Cadence and Altium, including working knowledge of Cadence Allegro for design review.
• Experience with FPGA- or MCU-based hardware design, including pin mapping, device selection, and evaluation of alternative SKUs against system requirements.
• Experience working with contract manufacturers, offshore manufacturing partners, mechanical and thermal teams, PCB vendors, quality, compliance, and supplier organizations.
• Experience designing complete high-speed channels that include ICs, sockets, connectors, cables, and customer system interfaces.
• Experience partnering with silicon characterization and post-silicon validation teams to ensure device performance is achievable in customer systems.
• Strong technical writing skills, including development of hardware specifications, validation reports, user guides, and other internal and customer-facing documentation.
• Startup experience and a proactive, hands-on, customer-focused approach to solving complex problems.

Salary range is $238,500 to $265,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Astera Labs’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.