Principal PCS/PMA RTL Design Engineer

Astera Labs; San Jose (CA); On-site; USD 185,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focusing on PCS and PMA logic for high-speed interconnects such as Ethernet, PCIe, UCIe, and UALink. You will translate microarchitectural specs into synthesizable RTL and collaborate with SerDes/verification, physical design, and firmware teams.

You will work on clock/data recovery, equalization, calibration, and multi-lane design, delivering robust designs through tapeout and silicon validation.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering required.
• 3+ years of relevant experience in digital ASIC/SoC/RTL design.
• Hands-on experience with Verilog or SystemVerilog RTL development and RTL debugging.

Responsibilities

• PCS/PMA RTL design and implementation for Ethernet, PCIe, UCIe, and UALink.
• Implement PCS functions: encoding/decoding, scrambling, alignment, deskew, lane reordering, gearboxes, FIFOs, rate adaptation.
• Implement forward error correction (RS-FEC/KP4, FEC framing, interleaving) and related control logic.
• Design PMA digital interface logic, including SerDes datapaths, CDR interfaces, and link-training control.
• Develop lane-level and multi-lane logic, including PRBS, loopback, and BIST features.
• Translate architectures into datapaths, control, state machines, and protocol logic; create reusable RTL modules.
• Integrate internal/third-party IP and follow established design methodologies.
• Support RTL reviews, lint, CDC/RDC checks, and multi-clock-domain considerations.
• Collaborate with verification and backend teams to ensure timing, power, and area goals.

Skills

RTL design

Verilog/SystemVerilog

High-speed protocols

Digital ASIC/SoC

Collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree preferred

Tools

Cadence Genus/Innovus

Synopsys Design Compiler/ICC2

Verilog tooling

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Principal PCS/PMA RTL Design Engineer

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs.

You will work with experienced architects and design engineers to translate microarchitectural specifications into robust, synthesizable RTL. You will collaborate closely with SerDes/analog, verification, physical design, DFT, firmware, systems, and validation teams to deliver reliable designs through synthesis, timing closure, tapeout, and silicon validation.

This is a hands-on opportunity for an engineer who wants to build expertise in multi-protocol, multi-lane PHY digital design and contribute to products that enable next-generation AI and cloud infrastructure.

Key responsibilities

PCS/PMA RTL design and implementation

• Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols.
• Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation.
• Implement forward error correction (e.g., RS-FEC/KP4, FEC framing, interleaving), plus the related error counters and status logic.
• Implement PMA digital interface logic, including SerDes datapath interfaces (PIPE, SerDes-facing parallel interfaces, UCIe PHY/raw-die interfaces), clock and data recovery (CDR) control interfaces, equalization and link-training control (e.g., PCIe LTSSM equalization, Ethernet auto-negotiation/link training), and calibration and adaptation control.
• Design lane-level and multi-lane logic, including lane bonding, polarity and lane reversal, PRBS generation/checking, loopback modes, and BIST features.
• Translate architectural and microarchitectural specifications into datapaths, control logic, state machines, register interfaces, and protocol logic.
• Design reusable, configurable RTL modules that support multiple protocols, data rates, and lane configurations.
• Integrate internal and third-party IP (including analog/mixed-signal PHY macros) while following established design and coding methodologies.
• Participate in design reviews and contribute to improvements in RTL quality, reuse, latency, performance, power, and area.

Verification and design quality

• Collaborate with design verification engineers to define functional requirements, test plans, and coverage goals, including protocol compliance (IEEE 802.3, PCI-SIG, UCIe, UALink specifications).
• Debug simulation failures using waveform analysis, assertions, regression results, and root-cause analysis.
• Support lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and RTL quality checks, with particular attention to multi-clock-domain PCS/PMA boundaries and asynchronous lane clocks.
• Participate in UVM-based verification activities and help resolve functional and integration issues.
• Support gate-level simulation and regression debug as required.

Synthesis, timing, and implementation

• Support logic synthesis, constraints development, and design implementation flows for high-speed, wide-datapath designs.
• Perform Static Timing Analysis (STA) and help identify and resolve setup, hold, clock, and interface timing issues, including at the SerDes and PHY boundaries.
• Support timing closure, power optimization, and PPA trade-offs in collaboration with synthesis, timing, and physical-design teams.
• Assist with DFT integration, scan requirements, low-power intent (including per-lane power states), ECOs, and implementation signoff.
• Review reports and debug issues from Cadence and/or Synopsys digital design flows.

Silicon and cross-functional collaboration

• Support block-level and subsystem-level integration through tapeout milestones.
• Collaborate with SerDes/analog, physical design, DFT, firmware, systems, packaging, and validation teams.
• Participate in silicon bring-up, link bring-up, interoperability and compliance testing, post-silicon debug, and failure analysis as opportunities arise.
• Document design decisions, issues, and technical solutions clearly for cross-functional stakeholders.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• Master's degree is preferred.
• 3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience.
• Hands-on experience with Verilog or SystemVerilog RTL development.
• Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.
• Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer.
• Experience with RTL simulation, debugging synthesis, and basic timing analysis.
• Familiarity with ASIC design flows and collaboration across design and verification teams.
• Strong communication skills and the ability to work effectively in a collaborative, fast-paced environment.
• Ability and willingness to work onsite in San Jose, California.

Preferred qualifications

• Direct experience designing PCS, PMA, or PHY digital logic for Ethernet (25G–224G per lane, 100G/200G/400G/800G/1.6T), PCIe (Gen4/5/6/7), UCIe, UALink, CXL, or similar standards.
• Experience with PAM4 signaling, FEC (RS-FEC/KP4, FLIT-mode FEC/CRC), lane deskew/alignment, link training, and equalization control.
• Familiarity with the PIPE specification, 802.3 Clause 73/72/136/162-series, PCIe LTSSM, and UCIe link training and sideband.
• Experience with multi-lane, multi-rate SerDes digital datapaths and clocking architectures.
• Familiarity with interconnect, networking, or data-center ASICs (retimers, switches, NICs, DPUs, SmartNICs, NoCs).
• Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2.
• Experience with STA using tools such as Synopsys PrimeTime or Cadence Tempus.
• Familiarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows.
• Experience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development.
• Experience with Python, Tcl, Perl, Shell, or other scripting languages for design and verification automation.
• Exposure to advanced-node CMOS design (e.g., 5nm/3nm), tapeout, silicon bring-up, or post-silicon validation, including BER measurements and lab debug.
• Experience working with physical-design teams on floorplanning, congestion, timing, power, and implementation challenges.

Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Astera Labs’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A 'disabled veteran' is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A 'recently separated veteran' means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An 'active duty wartime or campaign badge veteran' means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An 'Armed forces service medal veteran' means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.