Principal Design Verification Engineer – High Performance CPU Subsystem

SiFive, Inc.; Austin (TX); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Healthcare benefits

Retirement plans

Paid time off

Job summary

SiFive, Inc. is seeking a Principal Design Verification Engineer to lead the verification strategy for high-performance CPU subsystems, including out-of-order CPU core development and cache-coherent interconnect behavior.

The ideal candidate will have at least 12 years of experience in CPU functional verification and a strong grasp of CPU microarchitecture. This role offers a competitive benefits package, including healthcare and retirement plans.

Qualifications

• 12+ years of relevant experience in CPU/core or SoC functional verification.
• Direct experience with out-of-order core verification.
• Strong understanding of cache-coherent systems.

Responsibilities

• Lead verification strategy and execution for high-performance CPU subsystem development.
• Define verification strategies for complex CPU behaviors.
• Drive efficient failure analysis and root-cause debug.

Skills

CPU/core verification

Debug skills

CPU microarchitecture understanding

Verification methodology

Scripting and automation

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Principal Design Verification Engineer

SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for a high-performance CPU subsystem spanning both out-of-order CPU core development and cache-coherent interconnect/subsystem behavior.

Responsibilities

• Lead verification strategy and execution for high-performance CPU subsystem development, covering OoO core microarchitecture and coherent interconnect/subsystem behavior.
• Own verification planning, execution, debug, coverage analysis, and closure from block level through subsystem integration and signoff.
• Define verification strategies for complex CPU behaviors including branch prediction, instruction fetch, issue/dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
• Define verification strategy and closure criteria for coherent traffic, protocol correctness, ordering rules, backpressure, buffering behavior, arbitration, QoS, and error handling across cache-coherent interconnect paths.
• Drive verification across interface boundaries, bridges, and protocol adaptation paths, including conversion, buffering, and related subsystem-level data movement behavior.
• Develop high-value checkers, scoreboards, assertions, stimulus strategies, and coverage models to expose corner cases and improve bug-finding efficiency.
• Apply the right verification method for the problem, using simulation, formal techniques, and emulation to improve quality and accelerate turnaround.
• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve designs from a verification and debugability perspective.
• Drive efficient failure analysis and root‑cause debug across specification, RTL, test content, and verification infrastructure.
• Mentor engineers, influence team-wide methodology, and shape reusable verification approaches that benefit future generations of high-performance CPU subsystems.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with depth appropriate for a Principal / T6 role.
• Direct experience with out-of-order core verification and strong understanding of CPU microarchitecture.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow‑control semantics.
• Deep expertise in one or more CPU areas such as Frontend, Midcore, Load–Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into effective verification strategy and execution.
• Strong software development, scripting, and automation skills for building scalable DV infrastructure and workflows.

Preferred Qualifications

• Experience spanning both high-performance CPU core verification and coherent interconnect, cache, or memory-subsystem verification in large SoCs.
• Experience with subsystem integration, bridge-heavy designs, or protocol interactions across multiple interfaces.
• Experience using formal verification for bounded, interface-heavy, or high-risk microarchitectural problems.
• Experience using emulation to accelerate verification and improve turnaround on large CPU and subsystem verification workloads.
• Experience collaborating effectively with performance, compiler, software, formal, and system verification teams to close gaps from multiple perspectives.
• Demonstrated technical leadership through mentoring engineers, influencing methodology, and driving cross-team execution on complex verification efforts.

What Success Looks Like

• Verification plans capture the real architectural and microarchitectural risks early and completely.
• Difficult CPU and coherent-subsystem bugs are found early, debugged efficiently, and closed with durable fixes.
• Verification quality improves across the broader organization through stronger methodology, better technical guidance, and reusable infrastructure.
• Architecture, design, and DV teams rely on the engineer as a technical leader for the most complex verification challenges in high-performance CPU subsystem development.

Benefits

This role may be eligible for variable / incentive compensation and/or equity. It also includes a comprehensive, competitive benefits package that may include healthcare and retirement plans, paid time off, and more.

Legal and Equitable Employment Information

SiFive is an equal opportunity employer. SiFive is a champion of diversity and is committed to creating an inclusive environment for all employees. SiFive is an E‑Verify employer. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. This position requires a successful background and reference check and satisfactory proof of the right to work in the United States of America.