Principal Design Verification Engineer – CPU Core Frontend

SiFive, Inc.; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

SiFive, Inc. in Austin, Texas, seeks a Principal Design Verification Engineer to lead verification strategy for the CPU Core Frontend in a high‑performance out‑of‑order core.

You will define architecture‑aware strategies, identify microarchitectural risk early, and drive verification quality across the DV organization. You will mentor engineers, develop test plans and coverage, and coordinate with architects from feature definition through sign‑off, tackling memory management unit verification

Qualifications

• 12+ years in CPU/core or SoC functional verification.
• Direct experience with out‑of‑order CPU core verification.
• Deep expertise in CPU frontend verification (branch prediction and fetch).
• Strong knowledge of verification flow: test plans, stimulus, coverage.

Responsibilities

• Lead verification planning and execution for CPU frontend functionality (branch prediction, fetch).
• Define strategies, test plans, checkers, scoreboards, assertions, and coverage models.
• Drive verification of branch prediction structures and fetch behavior.
• Mentor engineers and shape reusable DV infrastructure and methodologies.
• Collaborate with architects from feature definition to sign‑off for frontend verification.

Skills

Frontend verification

Branch prediction

Instruction fetch

Verification strategy

Scripting fundamentals

Mentoring

Memory-management verification

CPU core verification

Education

BS, MS, or PhD in Electrical Engineering or related field

Tools

Simulation tools

Emulation

Job description

Role Overview

SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for the CPU Core Frontend in a high-performance out-of-order core. This senior tech‑lead role requires defining architecture‑aware verification strategy, identifying microarchitectural risk early, solving the hardest frontend verification problems, and raising verification quality across the CPU DV organization.

Responsibilities

• Lead verification planning and execution for CPU frontend functionality, focusing on branch prediction and instruction fetch behavior.
• Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for frontend microarchitecture and its corner cases.
• Drive verification of branch prediction structures and flows, including direction prediction, indirect target prediction, return prediction, predictor update/training behavior, redirect generation, recovery, and interaction with global history or related predictor state.
• Drive verification of instruction fetch behavior, including fetch packet correctness, PC sequencing, fetch ordering, ITLB/translation interactions, exception reporting, cache‑related fetch behavior, and redirect handling after misprediction or flush conditions.
• Partner with architects and designers from early feature‑definition stages to review specifications, identify ambiguity, and improve frontend debugability and verification completeness.
• Drive block‑level and core‑level verification closure for frontend features, including coverage analysis, gap identification, bug triage, and sign‑off readiness.
• Apply appropriate verification methods—simulation, formal techniques, and emulation—where appropriate for high‑risk or hard‑to‑observe frontend behaviors.
• Mentor engineers across the organization and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.
• Work on solving verification challenges of memory management units reused across several core generations, including hypervisor, virtualization, and guest virtualization.

What Success Looks Like

Frontend verification plans capture real architectural and microarchitectural risks early and completely. Difficult branch prediction, fetch, redirect, and recovery bugs are found early, debugged efficiently, and closed with durable solutions. Verification quality improves across the broader CPU DV organization through stronger methodology, reusable infrastructure, and clear technical leadership.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with substantial experience in high‑performance CPU verification appropriate for a Principal / T6 role.
• Direct experience with out‑of‑order CPU core verification and strong understanding of CPU microarchitecture.
• Deep expertise in CPU frontend verification, especially branch prediction and instruction fetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into an effective verification strategy and execution plan.
• Strong software and scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.
• 8+ years of direct experience in memory‑management verification, including hypervisor, virtualization, and guest virtualization scenarios.

Preferred Qualifications

• Experience verifying advanced frontend architectures or decoupled fetch/prediction pipelines in high‑performance CPU cores.
• Experience with branch prediction microarchitecture such as BTB‑style structures, target prediction, return prediction, global‑history‑based prediction, predictor training, and misprediction recovery.
• Experience using formal verification to target bounded, control‑heavy, or interface‑sensitive frontend problems.
• Experience using emulation or other acceleration techniques to improve turnaround on large CPU verification workloads.
• Experience collaborating across architecture, performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
• Demonstrated technical leadership through mentoring, methodology influence, and cross‑team execution on complex CPU verification efforts.

Benefits

In addition to base pay, this role may be eligible for variable or incentive compensation and/or equity. The role also qualifies for a comprehensive, competitive benefits package, which may include healthcare and retirement plans, paid time off, and more.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment for this position is also contingent on the company verifying that you have authorized access to export‑controlled technology under applicable export control laws, or that we successfully obtain any necessary export license(s) or other approvals.

Equal Employment Opportunity

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.