Principal Design Verification Engineer – High Performance CPU Subsystem

SiFive; Austin (TX); On-site; Full time

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC‑V to the highest performance and most data‑intensive applications. Our compute platforms enable leading technology companies to innovate, optimize, and deliver the most advanced solutions across AI, machine learning, automotive, data center, mobile, and consumer markets. The future of RISC‑V has no limits.

Job Description

The Role

Principal Design Verification Engineer leading verification strategy and execution for a high‑performance CPU subsystem spanning out‑of‑order core development and cache‑coherent interconnect behavior. This individual‑contributor role defines architecture‑aware verification strategy, identifies risks early, solves subsystem‑level problems, and raises verification quality across the organization.

Responsibilities

• Lead verification strategy and execution for high‑performance CPU subsystem development, covering OoO core microarchitecture and coherent interconnect/subsystem behavior.
• Own verification planning, execution, debug, coverage analysis, and closure from block level through subsystem integration and signoff.
• Define verification strategies for complex CPU behaviors including branch prediction, instruction fetch, issue/dispatch, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
• Define verification strategy and closure criteria for coherent traffic, protocol correctness, ordering rules, backpressure, buffering, arbitration, QoS, and error handling across cache‑coherent interconnect paths.
• Drive verification across interface boundaries, bridges, and protocol adaptation paths, including conversion, buffering, and related subsystem‑level data movement behavior.
• Develop high‑value checkers, scoreboards, assertions, stimulus strategies, and coverage models that expose corner cases and improve bug‑finding efficiency across core and uncore verification problems.
• Apply the right verification method—simulation, formal techniques, and emulation—to improve quality, accelerate turnaround, and strengthen debug efficiency on large subsystem workloads.
• Partner with architects and designers from early feature‑definition stages to review specifications, identify ambiguity, and improve designs from a verification and debugability perspective.
• Drive efficient failure analysis and root‑cause debugging across specification, RTL, test content, and verification infrastructure.
• Mentor engineers, influence team‑wide methodology, and shape reusable verification approaches that benefit future high‑performance CPU subsystems.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 12+ years of experience in CPU/core or SoC functional verification, with depth appropriate for a Principal/T6 role.
• Direct experience with out‑of‑order core verification and strong understanding of CPU microarchitecture.
• Strong understanding of cache‑coherent systems, on‑chip interconnects, memory subsystem behavior, and verification of ordering and flow‑control semantics.
• Deep expertise in one or more CPU areas such as Frontend, Midcore, Load‑Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into effective verification strategy and execution.
• Strong software development, scripting, and automation skills for building scalable DV infrastructure and workflows.

Preferred Qualifications

• Experience spanning both high‑performance CPU core verification and coherent interconnect, cache, or memory‑subsystem verification in large SoCs.
• Experience with subsystem integration, bridge‑heavy designs, or protocol interactions across multiple interfaces.
• Experience using formal verification for bounded, interface‑heavy, or high‑risk microarchitectural problems.
• Experience using emulation to accelerate verification and improve turnaround on large CPU and subsystem verification workloads.
• Experience collaborating effectively with performance, compiler, software, formal, and system verification teams to close gaps from multiple perspectives.
• Demonstrated technical leadership through mentoring engineers, influencing methodology, and driving cross‑team execution on complex verification efforts.

What Success Looks Like

• Verification plans capture real architectural and microarchitectural risks early and completely.
• Difficult CPU and coherent‑subsystem bugs are found early, debugged efficiently, and closed with durable fixes.
• Verification quality improves across the broader organization through stronger methodology, better technical guidance, and reusable infrastructure.
• Architecture, design, and DV teams rely on you as a technical leader for the most complex verification challenges in high‑performance CPU subsystem development.

Additional Information

This position requires successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment is contingent on verifying access to export‑controlled technology and, if not authorized, obtaining necessary export licenses.

In addition to base pay, the role may be eligible for variable or incentive compensation and/or equity. The role is eligible for a comprehensive, competitive benefits package that may include healthcare and retirement plans, paid time off, and more.

SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use the system to confirm employment eligibility of new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire.