Principal Design Validation & Test Architect

Celero Communications, Inc.; Irvine (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

Celero Communications, Inc. is seeking an experienced DVT Engineer to lead post-silicon validation for next‑gen coherent DSP ASICs in Irvine, CA.

You will drive silicon characterization and ensure customer-ready readiness, collaborating with architecture, RTL, firmware, and systems teams. The role involves defining validation strategy, building validation infrastructure, and enabling first silicon bring-up across multiple platforms.

Qualifications

• 8+ years of hands-on post-silicon validation and DVT experience.
• Experience bringing first silicon to production in networking, data center, AI, or HPC products.
• Strong understanding of silicon debug methodologies and root-cause analysis.
• Ability to lead validation strategy in a fast-paced startup environment.

Responsibilities

• Lead post-silicon validation and characterization from first silicon to production release.
• Develop comprehensive validation plans for functionality, performance, interoperability and reliability.
• Enable first silicon bring-up using JTAG, scan, and embedded debug features.
• Validate high-speed interfaces (PCIe, Ethernet, SerDes, CXL, SPI, I2C).
• Build Python-based automation for test execution, regression, and data analysis.
• Document validation results and production readiness reports.

Skills

Python programming

Post-silicon validation

Hardware debugging

Cross-functional collaboration

Leadership mindset

Education

Bachelor's or Master's in Electrical Engineering

Tools

Oscilloscopes

BERTs

Protocol analyzers

Ethernet/network analyzers

Logic analyzers

Power measurement equipment

Job description

Celero Communications, Inc. is seeking an experienced DVT Engineer to lead post-silicon validation for next‑gen coherent DSP ASICs in Irvine, CA.

You will drive silicon characterization and ensure customer-ready readiness, collaborating with architecture, RTL, firmware, and systems teams. The role involves defining validation strategy, building validation infrastructure, and enabling first silicon bring-up across multiple platforms.