Principal DFT Engineer — ASIC/SoC Test Architect

Celero Communications, Inc.; United States; Remote; USD 150,000 - 210,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal DFT Engineer to lead DFT efforts for ASIC/SoC designs in Irvine, CA.

You will architect and implement DFT solutions, drive signoff, and collaborate with RTL, verification, and physical teams to ensure robust testability. You will develop scan, ATPG, and MBIST strategies, validate fault coverage, and support manufacturing test readiness while contributing to silicon bring-up and yield improvements.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
• Results-driven engineer with strong debugging abilities.
• Comfortable working in fast-paced cross-functional environments.
• Passion for delivering high-quality silicon products.

Responsibilities

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST, and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

Skills

DFT engineering

Verilog/SystemVerilog

Python

Linux

Debugging

Cross-functional collaboration

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

Synopsys TestMAX/TetraMAX

DFT Compiler

Siemens Tessent

Cadence Modus

Job description

Celero Communications, Inc. is seeking a Principal DFT Engineer to lead DFT efforts for ASIC/SoC designs in Irvine, CA.

You will architect and implement DFT solutions, drive signoff, and collaborate with RTL, verification, and physical teams to ensure robust testability. You will develop scan, ATPG, and MBIST strategies, validate fault coverage, and support manufacturing test readiness while contributing to silicon bring-up and yield improvements.