Senior CAD Engineer, PPA & Physical Design

Ampere Computing; Santa Clara (CA); On-site; USD 195,000 - 292,000; Full time

Benefits offered by this job

Health insurance

401K retirement plan

Unlimited flextime

Paid holidays

Job summary

Ampere Computing is seeking a Principal CAD Engineer to lead high-performance physical design across multiple projects. You will drive PPA optimization from synthesis to sign-off and develop robust design flows for advanced nodes.

We expect strong experience in low power techniques (UPF/CPF), scripting (Python/Tcl), and Cadence Genus/Innovus, with a track record of delivering chip-scale designs and scalable CAD infrastructure. Join a team delivering energy-efficient AI compute.

Qualifications

• Proven experience driving PPA optimization across physical design flows – from synthesis to sign-off at advanced technology nodes.
• Success in delivering block or chip-level designs with aggressive PPA targets.
• Experience in low power design and implementation techniques using UPF/CPF.
• Proficiency in hierarchical P&R, floorplanning, pin-assignment, clock-distribution, critical-signal handling, hierarchical abstractions (black-box, ILM, etc.).
• Proficient in scripting using Tcl, Perl, Python, Makefile, etc.
• Expertise in developing scalable CAD infrastructure and automation frameworks for PPA regressions.
• Familiar with chip-finishing and sign-off processes including metal-fill, spare-cells, DFM, boundary-cell insertion, etc.
• Experience with EDA tools such as Cadence Genus, Innovus, Mentor Calibre, etc.
• Excellent communication, analytical and debugging skills.
• Electrical or Computer Engineering - Bachelor’s degree & 8 years of related experience; or Master’s degree & 6 years; or PhD & 3 years

Responsibilities

• Drive development and continuous improvement of synthesis and physical design methodology with a focus on maximizing Power, Performance and Area (PPA)
• Collaborate closely with implementation and physical design teams to optimize PPA metrics across multiple projects
• Analyze the impact of technology and design changes on PPA at block and full chip level
• Identify PPA bottlenecks and develop solutions that balance timing, area, power and routability
• Debug flow issues and implement robust automation for scalable deployment across various advanced technologies and design teams

Skills

PPA optimization

Scripting (Python/Tcl/Perl)

CAD infrastructure

Team collaboration

Analytical skills

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Cadence Genus

Cadence Innovus

Mentor Calibre

Job description

Ampere Computing is seeking a Principal CAD Engineer to lead high-performance physical design across multiple projects. You will drive PPA optimization from synthesis to sign-off and develop robust design flows for advanced nodes.

We expect strong experience in low power techniques (UPF/CPF), scripting (Python/Tcl), and Cadence Genus/Innovus, with a track record of delivering chip-scale designs and scalable CAD infrastructure. Join a team delivering energy-efficient AI compute.