Principal ASIC Design Engineer

Yoh Services LLC; Santa Clara (CA); On-site; USD 250,000 - 265,000; Full time

Benefits offered by this job

Medical benefits

HSA

Life & disability insurance

MetLife voluntary benefits

EAP

401K plan

Direct deposit

Referral bonuses

Training programs

Job summary

Yoh, a Day & Zimmermann company, seeks a Principal ASIC Design Engineer to own front-end RTL and microarchitecture for high-performance networking silicon. You will collaborate with architecture, verification, emulation, DFT, and physical design to translate product requirements into robust microarchitecture and production-ready RTL.

The ideal candidate brings hands-on RTL design leadership, multiple tapeouts, and deep expertise in PPA, timing, and design quality in a fast-paced environment.

Qualifications

• 5+ years of ASIC or SoC logic design experience with hands-on RTL development.
• Strong SystemVerilog experience and solid understanding of digital design fundamentals, CDC, synthesis, timing, and clocking.
• Experience defining microarchitecture and developing complex ASIC blocks from specification through implementation.

Responsibilities

• Define microarchitecture and implement synthesizable RTL for complex ASIC blocks and subsystems.
• Develop high-quality SystemVerilog designs optimized for performance, power, area, and timing.
• Partner with Design Verification and Emulation teams on test strategy, debug, coverage closure, and design intent.
• Work with Physical Design and DFT teams on synthesis, timing closure, area optimization, clocking, and test logic integration.
• Review design reports, identify architectural or RTL bottlenecks, and drive fixes through tapeout and silicon bring-up.

Skills

SystemVerilog

RTL design

Microarchitecture

Scripting languages

Education

BS/MS in Electrical Engineering, Computer Engineering, Computer Science

Tools

Python

Perl

Tcl

Job description

Principal ASIC Design Engineer RTL / Microarchitecture / High-Performance Networking

Overview Seeking a Principal ASIC Design Engineer to own front-end design for complex, high-performance silicon used in advanced networking and AI infrastructure. This role will work closely with architecture, verification, emulation, DFT, and physical design teams to translate product requirements into robust microarchitecture and production-ready RTL.

The ideal candidate is a hands-on technical leader with deep RTL design experience, multiple successful tapeouts, and a strong understanding of performance, power, area, timing, and design quality.

Key Responsibilities

• Define microarchitecture and implement synthesizable RTL for complex ASIC blocks and subsystems.
• Develop high-quality SystemVerilog designs optimized for performance, power, area, and timing.
• Partner with Design Verification and Emulation teams on test strategy, debug, coverage closure, and design intent.
• Work with Physical Design and DFT teams on synthesis, timing closure, area optimization, clocking, and test logic integration.
• Review design reports, identify architectural or RTL bottlenecks, and drive fixes through tapeout and silicon bring-up.

Required Qualifications

• 5+ years of ASIC or SoC logic design experience with strong hands-on RTL development.
• Strong SystemVerilog experience and solid understanding of digital design fundamentals, CDC, synthesis, timing, and clocking.
• Experience defining microarchitecture and developing complex ASIC blocks from specification through implementation.
• Ability to debug cross-functional issues with Verification, Emulation, Physical Design, and DFT teams.
• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.

Preferred Qualifications

• 12+ years of relevant experience with multiple successful ASIC tapeouts.
• Experience with Lint, CDC, RDC, formal verification, synthesis, STA, and front-end design methodology.
• Strong scripting skills using Python, Perl, Tcl, or similar languages.
• Experience analyzing timing, power, and area reports and making RTL or architectural changes to improve PPA.
• Exposure to silicon bring-up and post-silicon debug.
• Experience with high-performance networking ASICs, Ethernet switch silicon, packet processing, low-latency datapaths, NoC, SerDes integration, or AI infrastructure silicon.
• Background in switch ASICs, NICs, DPUs, network processors, or data center networking is a strong plus.

Estimated Min Rate: $250000.00/Annually

Estimated Max Rate: $265000.00/Annually

Benefits

• Medical, Prescription, Dental & Vision Benefits (for employees working 20+ hours per week)
• Health Savings Account (HSA) (for employees working 20+ hours per week)
• Life & Disability Insurance (for employees working 20+ hours per week)
• MetLife Voluntary Benefits
• Employee Assistance Program (EAP)
• 401K Retirement Savings Plan
• Direct Deposit & weekly epayroll
• Referral Bonus Programs
• Certification and training opportunities

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.