Senior ASIC CAD Engineer

Palo Alto Networks, Inc.; Santa Clara (CA); On-site; USD 130,000 - 180,000; Full time

Job summary

Palo Alto Networks, Inc. is seeking an experienced ASIC CAD Engineer in Santa Clara, California. In this role, you will be the vital link between front-end logic and design teams, focusing on Logic Synthesis, Static Timing Analysis, and Power Optimization.

The ideal candidate has over 10 years of experience and expert-level scripting skills. Join a pioneering team committed to innovation and excellence while driving the future of cybersecurity solutions.

Qualifications

• 10+ years of experience in ASIC front-end design and timing closure.
• Proven record of delivering clean netlists to foundries or ASIC vendors.
• Experience integrating design constraints for high-speed interfaces.
• Deep production experience with industry-standard tools.

Responsibilities

• Drive full-chip logic synthesis for optimal PPA over advanced nodes.
• Formulate master timing constraints and execute sign-off STA.
• Implement low-power strategies using UPF and analyze power profiles.
• Compile design handoff packages for vendor technical liaison.
• Enhance scripts for core implementation and validation flows.

Skills

Logic Synthesis

Static Timing Analysis (STA)

Power Optimization

Scripting (Perl, Python, Tcl)

Linux Shell

Education

BS/MS in Electrical Engineering

Tools

Synopsys Design Compiler

Cadence Genus

Job description

Our Mission

At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real‑world problems with cutting‑edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place.

Who We Are

In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values: Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real‑world problems and ideating beside the best and the brightest, we invite you to join us!

We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real‑time problem‑solving, stronger relationships, and the kind of precision that drives great outcomes.

Job Summary

Your Career

Join our ASIC team and help deliver the digital logic that powers our next‑generation firewall platforms. As an ASIC CAD Engineer you will be the critical bridge between frontend logic and physical design teams. Your primary mission is to take front‑end SystemVerilog code and successfully execute Logic Synthesis, Static Timing Analysis (STA), Power Optimization, and formal constraint management. You will also leverage your strong scripting skills to maintain and automate the underlying infrastructure, flows, and compute environments required to keep this design pipeline running at maximum efficiency.

Your Impact

• Drive full‑chip and block‑level logic synthesis, achieving optimal Power, Performance, and Area (PPA) over advanced process nodes.
• Formulate master timing constraints (SDC) and execute sign‑off Static Timing Analysis (STA) to resolve setup, hold, and clocking violations.
• Implement low‑power implementation strategies using UPF power intent architectures and analyze dynamic gate‑level power profiles.
• Act as the definitive technical liaison to our external P & R ASIC vendor, compiling comprehensive design handoff packages and reviewing post‑layout parasitic data to secure tape‑out closure.
• Develop and enhance Perl, Python and Tcl‑based scripts to automate our core front‑end implementation and validation flows.
• Support the maintenance of our ASIC CAD infrastructure and design flows required to keep this design pipeline running at maximum efficiency.

Your Experience

• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of experience in ASIC front‑end design, synthesis, and timing closure.
• Proven track record of delivering clean, verified netlists to foundries or external ASIC vendor layout teams.
• Proven track record of integrating, and configuring design constraints for IP blocks for high‑speed interfaces such as PCIe, Ethernet, or DDR.
• Deep production experience running standard industry tools like Synopsys Design Compiler/PrimeTime or Cadence Genus/Tempus.
• Expert‑level scripting capabilities using Perl, Python, Tcl, and Linux Shell environments.

Qualifications

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non‑sales roles) or base salary + commission target (for sales/com‑missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here.

Our Commitment

We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [e-mail].

Equal Opportunity Employment

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

EEO Disclosure

All your information will be kept confidential according to EEO guidelines.

Is role eligible for Immigration Sponsorship?: Yes