Principal Analog / Mixed-Signal IC Design Engineer

Calder Search; Waltham (MA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Calder Search is seeking an experienced Analog/Mixed-Signal IC Design Engineer (Senior to Principal) for the Greater Boston/Waltham area. The role is hybrid with three days onsite.

You will own circuits from topology through tapeout, including transistor-level design and layout cross-collaboration. Ideal candidates have strong fundamentals in analog/mixed-signal CMOS, multiple tapeouts, and proficiency with Cadence tools.

Qualifications

• Strong fundamentals in analog and mixed-signal CMOS IC design.
• Experience designing ADCs/DACs, PLLs, oscillators/VCOs, SerDes, regulators, references or related blocks.
• Multiple tapeout experiences with exposure to returned silicon.
• Strong understanding of small-signal analysis, feedback, stability, poles/zeros and transistor-level circuit behaviour.
• Experience with Cadence Virtuoso / Spectre or comparable IC design tools.
• PVT, Monte Carlo, PEX and corner-analysis experience.
• Understanding of analog layout, matching and parasitic effects.
• MS or PhD in Electrical Engineering, Microelectronics or a related discipline.

Responsibilities

• Transistor-level CMOS circuit design and simulation.
• Architecture and circuit trade-off analysis.
• Analog and mixed-signal block ownership.
• Schematic through layout, verification and tapeout.
• PVT, Monte Carlo, extracted and post-layout simulation.
• Silicon bring-up, characterization and debugging.
• Working across circuit areas rather than being restricted to one narrow speciality.

Skills

Analog CMOS design

Tapeout experience

Cadence tools

Circuit analysis

Education

MS or PhD in Electrical Engineering/Microelectronics

Tools

Cadence Virtuoso

Spectre

Job description

Analog / Mixed-Signal IC Design Engineer - Senior to Principal

Greater Boston / Waltham, MA | Hybrid - 3 days onsite

A well-funded semiconductor startup is building a fundamentally new computing architecture based on thermodynamic computing - using the natural stochastic behaviour of CMOS devices as a computational resource rather than something to eliminate.

The company is expanding its analog/mixed-signal IC team as it develops the next generation of custom silicon, with multiple chips moving through architecture and development.

This is an opportunity for experienced IC designers who want significantly more technical ownership than is typically available within a large semiconductor organisation.

Depending on experience, hires can be made at Senior or Principal level.

What you'll work on

You’ll own analog and mixed-signal circuits from initial architecture through silicon, including:

• Transistor-level CMOS circuit design and simulation
• Architecture and circuit trade-off analysis
• Analog and mixed-signal block ownership
• Schematic through layout, verification and tapeout
• PVT, Monte Carlo, extracted and post-layout simulation
• Silicon bring-up, characterization and debugging
• Working across circuit areas rather than being restricted to one narrow speciality

The environment is highly hands-on. Engineers are expected to understand their circuits from device/transistor level through block and system level, and to be comfortable getting involved in physical implementation and layout where required.

What we're looking for

You’ll likely have:

• Strong fundamentals in analog and mixed-signal CMOS IC design
• Experience designing circuits such as ADCs/DACs, PLLs, oscillators/VCOs, SerDes, regulators, references, amplifiers or related mixed-signal blocks
• Multiple tapeout experiences with exposure to returned silicon
• Strong understanding of small-signal analysis, feedback, stability, poles/zeros and transistor-level circuit behaviour
• Experience with Cadence Virtuoso / Spectre or comparable IC design tools
• PVT, Monte Carlo, PEX and corner-analysis experience
• Understanding of analog layout, matching and parasitic effects
• MS or PhD in Electrical Engineering, Microelectronics or a related discipline

Experience in advanced CMOS nodes, ultra-low-power design, subthreshold/weak-inversion circuits, precision analog or unconventional compute architectures is particularly interesting, but isn’t essential.

We're deliberately keeping the level flexible.

Senior-level engineers will typically have around 3-6+ years of relevant analog/mixed-signal IC design experience, multiple tapeouts and evidence of independently owning circuits.

Principal-level engineers will bring deeper architectural ownership and a track record of taking complex mixed-signal designs from concept through tapeout and silicon.

We're more interested in technical depth and ownership than job title.

The opportunity

This isn't a role maintaining another generation of an established product.

You’ll be joining a small IC team developing a new computing architecture, with the opportunity to influence circuits and silicon while the technology is still being defined.

If you're a strong transistor-level designer who enjoys understanding why a circuit behaves the way it does, rather than simply running established design flows, we'd like to hear from you.