Senior Layout Design Engineer – CMOS/BiCMOS Expert

SiTime Corporation; États-Unis; À distance; USD 140 000 - 190 000; Plein temps

Avantages offerts par ce poste

Quarterly bonus

Equity grants

Résumé du poste

SiTime Corporation seeks a Sr. Layout Design Engineer to lead top-level chip-planning and create block-level layouts for CMOS and BiCMOS circuits. You’ll coordinate work with offshore designers, train junior engineers, and contribute to standard layout methodologies across sites to achieve high layout quality.

You will interface with global teams, drive floor-planning and design constraints, and support tape-out while continuously refining workflows and processes for efficiency and reliability.

Qualifications

• BA/BS degree in Layout Design or related field or equivalent experience.
• 10 years’ experience with layout design for analog and full-custom digital blocks.
• Experience TSMC 180nm, 65nm, 22nm process technologies.
• Proficient in Cadence Virtuoso design environment.
• Solid debugging of DRC/LVS/ERC with Cadence PVS or Mentor Calibre.
• Understanding of parasitic, matching, crosstalk, latch-up, IR drop, EM, and NTN isolation.
• Ability to optimize layout for area and power distribution across multiple sites.

Responsabilités

• Remote interfacing with local and global design and layout teams in multiple centers across time zones.
• Lead top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, and standard cell layouts for CMOS/BiCMOS.
• Perform schematic-driven layout and design constraints.
• Design die-area efficient layouts per circuit requirements.
• Perform floor-planning, power line planning, shielding, and device-matching layout.
• Verify layouts (DRC, LVS, ERC) and support tape-out.

Connaissances

Layout design

Team coordination

Mentoring juniors

Problem solving

Formation

BA/BS in Layout Design or related field

Outils

Cadence Virtuoso

Mentor Calibre

Description du poste

SiTime Corporation seeks a Sr. Layout Design Engineer to lead top-level chip-planning and create block-level layouts for CMOS and BiCMOS circuits. You’ll coordinate work with offshore designers, train junior engineers, and contribute to standard layout methodologies across sites to achieve high layout quality.

You will interface with global teams, drive floor-planning and design constraints, and support tape-out while continuously refining workflows and processes for efficiency and reliability.