Principal Analog IC Design Engineer, High Speed SerDes

Cadence; San Jose (CA); On-site; USD 137,000 - 254,000; Full time

Job summary

Cadence in California seeks a Principal Analog IC Designer to lead the design and verification of analog/mixed-signal circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

The role requires a minimum of 7 years in CMOS SerDes or high-speed I/O IC design, deep knowledge of jitter and signal equalization, and proficiency with CAD tools for simulation, layout, and verification, including Cadence platforms. Experience at >10Gbps in <28nm nodes is a plus.

Qualifications

• 7+ years of experience in CMOS SerDes or high-speed I/O IC design and development.
• Thorough understanding of jitter and signal equalization techniques.
• Proficient design experience in SerDes blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, ADC and DAC, Bias and Bandgap, and Voltage Regulators.
• Experience with CAD tools for circuit simulation, layout, and physical verification.
• Cadence tool experience, lab test experience, and design at >10Gbps and <28nm technologies.
• MS or PhD in EE.

Responsibilities

• Lead the design and development of analog/mixed-signal IC blocks from concept/spec through verification.
• Collaborate with cross-functional teams to meet customer specifications.
• Apply jitter and equalization techniques to optimize performance across processes and environments.

Skills

CMOS SerDes

High-speed I/O design

Jitter control

Signal equalization

SerDes blocks knowledge

Cadence tools

Lab testing experience

Circuit simulation

Education

MS in EE

PhD in EE

Tools

Cadence tools

SPICE/Simulation

Verification tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

• Candidate’s background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development.
• Working knowledge of a set of common SerDes standards and their electrical requirements is a plus.
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification
• Cadence tool experience, lab test experience, and design experience at >10Gbps and in <28nm technologies are a plus
• MS or PhD in EE

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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