Principal Advanced Packaging Engineer — Optical Chips

Astera Labs; San Jose (CA); On-site; USD 205,000 - 260,000; Full time

Job summary

Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. This senior individual contributor role sets technical direction and drives packaging technology development for NPO and CPO products.

Responsibilities include defining wafer-, panel-, and die-level packaging flows, driving EIC-to-PIC integration, material qualification, and collaboration with OSATs, tool vendors, and suppliers to advance packaging capabilities.

Qualifications

• 8+ years in semiconductor packaging with leadership.
• Expertise in 2.5D/3D, flip-chip, TSV, RDL.
• Experience with EIC/PIC integration.
• OSAT equipment and materials qualification experience.
• PDK development and packaging design rules.
• Yield, reliability and SPC/Cpk methodologies knowledge.

Responsibilities

• Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
• Define and optimize wafer-, panel-, or die-level packaging processes.
• Drive EIC-to-PIC integration and broader optical device integration efforts.
• Select and qualify packaging materials for advanced packaging.
• Collaborate with OSAT, tool vendors, and material suppliers to advance packaging.
• Characterize and improve yield, reliability, and process capability for NPO and CPO packages.
• Develop and maintain packaging PDKs and design rules for NPO and CPO products.

Skills

Advanced packaging

Semiconductor packaging

2.5D/3D integration

EIC/PIC integration

Packaging flows

Education

Engineering degree (EE/Materials/Mechanical)

Job description

Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. This senior individual contributor role sets technical direction and drives packaging technology development for NPO and CPO products.

Responsibilities include defining wafer-, panel-, and die-level packaging flows, driving EIC-to-PIC integration, material qualification, and collaboration with OSATs, tool vendors, and suppliers to advance packaging capabilities.