Optical Chip Packaging Lead: 2.5D/3D, CPO/NPO

Astera Labs; San Jose (CA); On-site; USD 205,000 - 260,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Astera Labs in San Jose, CA seeks a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. Focus areas include 2.1D, 2.5D, and 3D integration, and defining wafer-, panel-, or die-level process flows.

You will drive EIC-to-PIC integration, select and qualify materials, and partner with OSATs and vendors to advance packaging development. A strong track record in advanced packaging and packaging design rules is required.

Qualifications

• Experience in advanced packaging engineering with leadership.
• Deep expertise in 2.5D/3D integration and related packaging processes.
• Experience with silicon photonics chip packaging and EIC/PIC integration.
• Hands-on with underfill, molding compounds, dielectrics, adhesives, or optical encapsulants.
• Proven track record with OSATs and packaging equipment suppliers.

Responsibilities

• Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
• Define and optimize wafer-, panel-, or die-level packaging process flows.
• Drive EIC-to-PIC integration and broader optical device integration efforts.
• Select and qualify packaging materials for advanced packaging.
• Partner with OSATs, tool vendors, and material suppliers to advance equipment, process, and materials.
• Characterize and improve yield, reliability, and performance for packages.
• Develop and maintain packaging PDks and design rules for NPO/CPO products.

Skills

Advanced packaging

Semiconductor packaging

2.5D/3D integration

Yield analysis

OSAT collaboration

Packaging design rules

Wafer/panel/die-level flows

Education

B.S./M.S./Ph.D. in Electrical Engineering or related fields

Tools

PDK development

Job description

Astera Labs in San Jose, CA seeks a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. Focus areas include 2.1D, 2.5D, and 3D integration, and defining wafer-, panel-, or die-level process flows.

You will drive EIC-to-PIC integration, select and qualify materials, and partner with OSATs and vendors to advance packaging development. A strong track record in advanced packaging and packaging design rules is required.