Mixed-Signal Verification Engineer (Analog & Digital)

Intel Corporation; Hillsboro (OR); Hybrid; USD 122,000 - 200,000; Full time

Benefits offered by this job

Hybrid work model

Competitive pay

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel is seeking an experienced verification engineer in Oregon to perform functional verification of mixed-signal logic and to develop comprehensive verification environments. You will design test benches, run system-level simulations, and collaborate with analog and digital teams to ensure designs meet specifications.

Ideal candidates will have HDL experience (VHDL/Verilog/SystemVerilog), strong debugging skills, and a track record of verification success in presilicon workflows.

Qualifications

• Bachelor's or Master's degree in a related field with relevant experience.

Responsibilities

• Perform functional verification of mixed-signal logic components and analog behavioral modeling.
• Develop IP verification plans, test benches and verification environment.
• Execute verification plans, run system simulations, analyze power and timing to uncover bugs.
• Replicate, root cause and debug issues in presilicon environments.
• Collaborate with digital/analog architects, RTL developers, and physical design teams to meet goals.
• Document test plans and lead technical reviews with design teams.
• Maintain and improve verification infrastructure and methodology.

Skills

Digital logic

Design debugging

Education

Bachelor's Degree in Electrical/Computer Engineering or related field

Master's Degree in Electrical/Computer Engineering or related field

Tools

VHDL/Verilog/SystemVerilog

Testbench development (OVM/UVM)

Job description

Intel is seeking an experienced verification engineer in Oregon to perform functional verification of mixed-signal logic and to develop comprehensive verification environments. You will design test benches, run system-level simulations, and collaborate with analog and digital teams to ensure designs meet specifications.

Ideal candidates will have HDL experience (VHDL/Verilog/SystemVerilog), strong debugging skills, and a track record of verification success in presilicon workflows.