Pre-Silicon IP Verification Engineer - Clock Gen Expert

Intel Corporation; Boxborough (MA); Híbrido; USD 122.000 - 173.000; Jornada completa

Descripción de la vacante

Intel Corporation is seeking an IP Design Verification Engineer to join the Central Engineering Group. You will develop verification environments for clock generator IPs such as PLL/FLL, implement tests, and debug pre-silicon issues throughout the product development lifecycle.

You will collaborate with architects, RTL and analog teams to ensure rigorous verification coverage and high-quality IP delivery for Intel’s advanced designs. The role supports a hybrid work model in the US.

Formación

• Bachelor's degree in Electrical or Computer Engineering with 4+ years of relevant experience.
• Master's degree with 3+ years of relevant experience.
• PhD with 1+ years of relevant experience.

Responsabilidades

• Develop test benches, verification environments, and tests using SystemVerilog and UVM.
• Perform functional verification for clock generator IPs (PLL and FLL).
• Maintain and refine verification infrastructure and methodologies for multiple IP generations.
• Debug and root-cause pre-silicon issues within the verification environment.
• Document test plans and participate in technical reviews with design teams.
• Collaborate with architects, RTL developers, and analog design teams to enhance verification.
• Lead Mixed Signal Validation activities, including AMS simulations and schematic debugging.
• Contribute to architectural and microarchitectural feature definitions for IP design.

Conocimientos

SystemVerilog

UVM

Python

Perl

Cross-functional collaboration

Educación

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Descripción del empleo

Intel Corporation is seeking an IP Design Verification Engineer to join the Central Engineering Group. You will develop verification environments for clock generator IPs such as PLL/FLL, implement tests, and debug pre-silicon issues throughout the product development lifecycle.

You will collaborate with architects, RTL and analog teams to ensure rigorous verification coverage and high-quality IP delivery for Intel’s advanced designs. The role supports a hybrid work model in the US.