Power Management Architect for High-Performance RISC-V SoCs

SiFive, Inc.; Austin (TX); On-site; USD 110,000 - 190,000; Full time

Benefits offered by this job

Flexible PTO

Health, Vision and Dental benefits

401(k) plan

Employee stock options

Job summary

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design PM, reset and clocking solutions for RISC-V CPU and SoC IP. You will work in a fast-paced team turning hardware into highly configurable IP.

You will collaborate with architecture, design verification, and software teams to meet frequency, area and power goals, with a focus on DVFS, DFT, and RTL quality checks. BS/MS in EE/CE/CS preferred.

Qualifications

• 3+ years in CPU/SoC clocking, reset, and power-management logic.
• Experience in high-performance, energy-efficient CPU/SoC designs.
• Proficiency with RTL design in Verilog, SystemVerilog, or VDHL.
• Knowledge of RTL quality checks (Lint, CDC, RDC).
• Team-oriented with strong collaboration skills.
• BS/MS in EE/CE/CS or related field.

Responsibilities

• Understand and define power management requirements with architecture team.
• Architect, design and implement core clocking, reset and PM solutions.
• Microarchitecture development and documentation.
• Sandbox verification and test plan development with verification team.
• Work with physical implementation team to meet frequency/area/power goals.
• Collaborate with software team to enable PM features.

Skills

CPU clocking

SoC clocking

Power management

RTL design

DVFS

DFT/MBIST

RTL quality checks

AMBA AXI/AHB/APB

RISC-V knowledge

Git/Jira/Confluence

Scala/Chisel/Bluespec

Education

BS/MS in EE/CE/CS

Tools

Verilog/SystemVerilog/VDHL

Job description

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design PM, reset and clocking solutions for RISC-V CPU and SoC IP. You will work in a fast-paced team turning hardware into highly configurable IP.

You will collaborate with architecture, design verification, and software teams to meet frequency, area and power goals, with a focus on DVFS, DFT, and RTL quality checks. BS/MS in EE/CE/CS preferred.