Post-Silicon ASIC Verification Intern - Hybrid Role

Hewlett Packard Enterprise; Roseville (CA); Ibrido; USD 48.000 - 56.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health benefits

Professional development

Inclusive culture

Descrizione del lavoro

Hewlett Packard Enterprise Development LP is seeking an ASIC Post-Si Verification Engineering Intern in Roseville, CA. You will collaborate with the ASIC/VLSI team on next-generation networking chips, with a summer project aligned to current or future ASIC development efforts.

The role involves working with senior team members on RTL/Physical Design, verification, and tool development. The position is hybrid, with in-office expectations and opportunities for learning across multiple assignments.

Competenze

• Pursuing a Bachelor's or Master's degree in a technical field (CE/CS/EE).
• At least 3rd year of engineering coursework completed.
• Basic programming or scripting knowledge (Verilog, SystemVerilog, Python, PERL, TCL, C, C++).

Mansioni

• RTL/Physical design learning and support.
• Pre-Silicon verification and post-Silicon verification tasks.
• Formal verification, script or tool development, and scheduling/documentation duties.
• Various assignments based on student skills and business needs.

Conoscenze

Verilog

SystemVerilog

Python

PERL

TCL

C

C++

Formazione

Bachelor's or Master's in Computer Engineering/CS/EE

Descrizione del lavoro

Hewlett Packard Enterprise Development LP is seeking an ASIC Post-Si Verification Engineering Intern in Roseville, CA. You will collaborate with the ASIC/VLSI team on next-generation networking chips, with a summer project aligned to current or future ASIC development efforts.

The role involves working with senior team members on RTL/Physical Design, verification, and tool development. The position is hybrid, with in-office expectations and opportunities for learning across multiple assignments.