Aspiring ASIC Engineer Intern: Design, Verification, or Tools

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 48,000 - 56,000; Full time

Job summary

Hewlett Packard Enterprise Development LP in Sunnyvale, California, invites you to join our ASIC team as an intern. You will gain hands-on experience in cutting-edge semiconductor development by focusing on ASIC Design, Verification, or Tools & Methodologies under the guidance of senior engineers.

This internship emphasizes practical RTL design with SystemVerilog, testbenches with UVM, and automation to accelerate workflows.

Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science.
• Coursework in Digital Logic Design, Computer Architecture, or VLSI Design is highly desirable.
• Familiarity with SystemVerilog, UVM, and basic Python or C++ knowledge.
• Interest in ASIC design, verification, or tools and methodologies.

Responsibilities

• Contribute to ASIC Design, Verification, or Tools & Methodologies based on chosen focus.
• Assist RTL design using SystemVerilog and help in synthesis, linting, and reviews.
• Develop and maintain testbenches with SystemVerilog and UVM.
• Participate in automation efforts and tooling improvements.

Skills

SystemVerilog

UVM

Python

C++

EDA tools

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

EDA tools for physical design

Emulation platforms

Job description

Hewlett Packard Enterprise Development LP in Sunnyvale, California, invites you to join our ASIC team as an intern. You will gain hands-on experience in cutting-edge semiconductor development by focusing on ASIC Design, Verification, or Tools & Methodologies under the guidance of senior engineers.

This internship emphasizes practical RTL design with SystemVerilog, testbenches with UVM, and automation to accelerate workflows.