Pixel IP Design Engineer for SoC Performance

Socket.dev

Sunnyvale (CA)

On-site

USD 180,000 - 320,000

Full time

14 days+

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Job summary

Apple is seeking an ASIC Design Engineer for the Pixel IP design team. You will be responsible for complex subsystem integration and implementation, writing RTL with assertions, and optimizing for high performance and low power.

You will collaborate with architecture, design, and verification teams to ensure robust functionality and timely delivery. A strong background in IP/SoC design and mult-domain clocking is required.

Qualifications

  • Bachelor's degree required with 10+ years of relevant experience.
  • Strong experience in IP/SoC design, integration at chip or subsystem level.
  • Knowledge of ASIC/FPGA design methodology, timing closure, and floorplanning.
  • Familiarity with multiple clock and reset domains and AMBA protocols (AXI/AHB/APB).
  • Experience with UPF power intent and scripting languages (Python/Perl/TCL).
  • Excellent collaboration and communication skills.

Responsibilities

  • Integrate and implement complex subsystems for Pixel IP design.
  • Write RTL with assertions and cover points for high performance, low power designs.
  • Collaborate with architecture, design, and verification teams to ensure functionality.
  • Work with physical design to optimize timing, area, and power in silicon.
  • Coordinate with cross-functional teams to deliver on project milestones.

Skills

IP/SoC design
ASIC/FPGA design
clock domain management
AMBA protocols
UPF power intent
scripting (Python|Perl|TCL)

Education

Bachelor's degree

Tools

Python
Perl
TCL

Job description

Apple is seeking an ASIC Design Engineer for the Pixel IP design team. You will be responsible for complex subsystem integration and implementation, writing RTL with assertions, and optimizing for high performance and low power.

You will collaborate with architecture, design, and verification teams to ensure robust functionality and timely delivery. A strong background in IP/SoC design and mult-domain clocking is required.

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