Physical Design Engineer

ACL Digital; San Diego (CA); Presencial; USD 140.000 - 190.000; Jornada completa

Descripción de la vacante

ACL Digital is seeking a Physical Design Engineer to transform synthesized netlists into manufacturing-ready silicon across cutting-edge mobile, automotive, compute, and AI SoCs. You will work on 5nm/3nm nodes, performing floorplanning, CTS, routing, SI/EM mitigation, and PPA-optimized sign-off.

Responsibilities include power integrity, DV checks, and cross-functional collaboration with RTL, DFT, CAD, and foundry teams. Strong scripting skills and experience with a full flow are essential.

Formación

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communications, VLSI Design, Computer Engineering, or related field.
• 0–7 years experience in ASIC physical design/STA for progression paths.
• Experience with low-power design flows and UPF/CPF preferred.

Responsabilidades

• Execute full physical design flows including floorplanning, placement, CTS, routing, and post-route optimizations.
• Perform multi-corner, multi-mode STA and timing sign-off.
• Implement low-power methodologies and analyze IR-drop and EM.
• Run DRC/LVS/ERC and ensure foundry compliance.
• Collaborate with RTL, DFT, CAD, and architecture teams to optimize PPA trade-offs.
• Develop automation scripts to speed up flows and reduce bottlenecks.

Conocimientos

Scripting & automation

Flow customization

CMOS fundamentals

Multi-core/SoC awareness

Educación

Bachelor’s or Master’s degree in Electrical Engineering or related field

Herramientas

Synopsys ICC2 / Fusion Compiler

Cadence Innovus

Synopsys PrimeTime / PrimeTime-SI

Cadence Tempus

Ansys RedHawk / RedHawk-SC

Cadence Voltus

Siemens Calibre (nmDRC, nmLVS, PERC)

Synopsys IC Validator

Descripción del empleo

Duration : 12 Months

Role Overview

As a Physical Design Engineeryou are responsible for transforming high-performance, low-power digital designs from synthesized netlists into manufacturing-ready silicon (Netlist-to-GDSII). You will work on cutting-edge mobile, automotive, compute (Snapdragon/Oryon CPU, Adreno GPU, NPU, and modem), and AI SoCs on advanced foundry nodes (e.g., 5nm, 3nm, and below).

Key Responsibilities

• Execute complete physical design flows including partition-level and full-chip floorplanning, power grid synthesis, placement, Clock Tree Synthesis (CTS), routing, and post-route optimization.
• Timing & Signal Integrity Closure: Perform multi-corner, multi-mode (MCMM) Static Timing Analysis (STA), constraint validation, setup/hold closure, signal integrity (SI) glitch/crosstalk mitigation, and clock-skew optimization.
• Power & IR-Drop Optimization: Implement low-power methodologies (UPF/CPF, power gating, multi-Vt, voltage domains) and drive static/dynamic IR-drop and electromigration (EM) analysis and remediation.
• Physical Verification & Sign-off: Run and debug Design Rule Checks (DRC), Layout Versus Schematic (LVS), Antenna, Electrical Rule Checks (ERC), and dummy metal fill to meet stringent external foundry requirements.
• Cross-Functional Collaboration: Partner with RTL design, DFT (Design-for-Test), CAD, architecture, and foundry integration teams to deliver optimal Power, Performance, and Area (PPA) trade-offs.
• Flow & Automation Development: Develop and maintain automation scripts to enhance turn-around time (TAT), improve methodology robustness, and resolve routing/timing bottlenecks.

Required Qualifications & Skills

• Place & Route: Synopsys ICC2 / Fusion Compiler or Cadence Innovus.
• Timing Sign-off: Synopsys PrimeTime / PrimeTime-SI or Cadence Tempus.
• Power/Reliability: Ansys RedHawk / RedHawk-SC or Cadence Voltus.
• Physical Verification: Siemens Calibre (nmDRC, nmLVS, PERC) or Synopsys IC Validator.
• Semiconductor Fundamentals: Solid grasp of CMOS digital logic, FinFET/GAAFET technology characteristics, standard cell libraries, and RC parasitics.
• Low-Power Design: Practical experience with UPF/CPF, multi-voltage domains, retention cells, and power switch fabrics.
• Scripting & Automation: Strong scripting skills in Tcl, Python, Perl, and Unix/Linux shell for flow customization and data mining.

Education & Experience

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, VLSI Design, Computer Engineering, or a related field.

Experience Levels:

• Engineer: 0–3 years of experience in ASIC physical design/STA.
• Senior Engineer: 3–7 years with proven block-level ownership and tape-out experience on FinFET nodes.
• Staff / Principal / Lead Engineer: 8+ years leading full-chip assembly, hierarchy planning, complex SoC integration, and sign-off closure.

Preferred Qualifications

• Hands-on tape-out track record on sub-7nm (5nm/4nm/3nm) advanced process nodes.
• Experience with high-frequency CPU cores, GPU blocks, or high-speed interface subsystems (PCIe, LPDDR, USB).
• Familiarity with Machine Learning/AI-driven PnR tool flows and automated PPA closure techniques