Implementation Lead

Oho Group; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

OHO Group in San Francisco is seeking a Physical Implementation Lead to own the end-to-end physical design of custom ASICs for AI workloads. You will shape architecture, set layout strategy, and collaborate with AI/EDA teams.

You will drive automation and reinforcement-learning based optimization, supervising sign-off (STA/DRC/LVS/EM/IR) on advanced nodes to deliver high-PPA silicon.

Qualifications

• 5–10 years of physical-design experience.
• Experience integrating AI-enabled design-optimisation tools into production flows.
• Strong understanding of reinforcement-learning principles for EDA and layout.
• Proven expertise in physical sign-off (STA, DRC, LVS, EM/IR).
• Expert-level Python and Tcl for automation and infrastructure.

Responsibilities

• Deliver physical implementation for high-throughput, low-latency accelerators, optimised for KPIs.
• Define and drive layout strategy for IP and large on-chip SRAM.
• Lead deployment of AI-driven design-optimisation engines to automate macro placement and clock/power networks.
• Address physical-design challenges with AI workloads, including IR-drop and clock-tree synthesis.
• Apply reinforcement-learning principles across backend stages to drive optimization.

Skills

Physical design

AI-enabled design optimization tools

Reinforcement learning

Python

Tcl

Tools

Python

Tcl

Job description

Physical Implementation Lead - San Francisco - Stealth Startup

A fast-growing semiconductor technology company is developing an AI-driven chip-design platform. The team combines deep expertise across AI, semiconductor architecture, physical design and chip development, with a focus on building highly automated approaches to custom silicon development.

They're looking for an engineering leader to drive physical implementation for custom ASICs. This is an end-to-end technical leadership role setting up architecture, collaborating with the wider team and eventually building out your own too.

Core Responsibilities

• Deliver physical implementation for high-throughput, low-latency accelerators, optimised against key design KPIs.
• Define and drive layout strategy for IP, high-bandwidth interfaces, large on-chip SRAM and register structures.
• Lead deployment of AI-driven design-optimisation engines to automate macro placement, optimise clock and power distribution networks, and maximise PPA.
• Address physical-design challenges associated with AI workloads, including dynamic IR-drop, thermal-density mitigation and multi-GHz clock-tree synthesis.
• Apply reinforcement-learning principles across backend implementation stages to drive design optimisation.

Required Qualifications

• 5–10 years of physical-design experience, with a track record of taking complex, large-die SoCs or compute subsystems through tape-out.
• Hands-on experience integrating AI-enabled design-optimisation tools into production implementation flows.
• Strong understanding of reinforcement-learning principles, including reward functions and optimisation techniques relevant to EDA and layout density.
• Proven expertise in physical sign-off, including STA, DRC, LVS and EM/IR on advanced process nodes.
• Expert-level Python and Tcl skills for developing and automating custom infrastructure and layout-iteration flows.

Ideal Candidate

• Strong technical ownership across the physical-design flow, from implementation strategy through sign-off.
• Experience working on large, performance-critical AI, compute or accelerator designs.
• Comfortable operating at the intersection of physical design, automation and AI-driven optimisation.
• Hands-on engineering mindset with the ability to solve complex backend challenges and drive execution.