Physical Design Intern: ASIC Layout & PPA

SK hynix memory solutions America Inc.; San Jose (CA); On-site; USD 48,216 - 61,992; Part time

Job summary

SK hynix memory solutions America Inc. is seeking a Physical Design Intern in San Jose, California. You will be part of a talented team working on next‑generation SSD controller chips, transforming RTL designs into physical layouts and gaining hands-on experience in the ASIC design flow.

The ideal candidate is pursuing a Bachelor's or Master's degree in Electrical or Computer Engineering, possesses foundational knowledge in VLSI design, and has experience with scripting languages. A competitive compensation of $35/hr - $45/hr is offered.

Qualifications

• Currently pursuing a degree in Electrical Engineering or related field.
• Foundational understanding of VLSI design and CMOS circuit design.
• Familiarity with ASIC physical design flow.

Responsibilities

• Execute physical design implementation flows including floorplanning and placement.
• Perform static timing analysis and resolve timing violations.
• Run design rule checks and ensure design integrity.

Skills

VLSI design concepts

CMOS circuit design

Digital logic

Scripting languages (Python, Perl, TCL)

Analytical and problem-solving

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Synopsys ICC2

Cadence Innovus

Static Timing Analysis tools (PrimeTime, Tempus)

Job description

SK hynix memory solutions America Inc. is seeking a Physical Design Intern in San Jose, California. You will be part of a talented team working on next‑generation SSD controller chips, transforming RTL designs into physical layouts and gaining hands-on experience in the ASIC design flow.

The ideal candidate is pursuing a Bachelor's or Master's degree in Electrical or Computer Engineering, possesses foundational knowledge in VLSI design, and has experience with scripting languages. A competitive compensation of $35/hr - $45/hr is offered.