ASIC Digital Design Intern

SK hynix memory solutions America Inc.; San Jose (CA); On-site; USD 48,216 - 61,992; Part time

Job summary

SK hynix memory solutions America Inc. is seeking an intern focused on ASIC design. You will assist engineers with RTL review, DFT activities, and run synthesis and timing analysis. The ideal candidate is pursuing a degree in Electrical or Computer Engineering, with a solid foundation in digital logic.

This role provides hands-on experience in a collaborative environment, with a compensation rate of $35/hr – $45/hr and mentorship from experienced engineers.

Qualifications

• Pursuing a Bachelor’s degree in Electrical Engineering or similar.
• Basic understanding of digital logic and familiarity with Verilog/SystemVerilog.
• Strong attention to detail with structured workflows.

Responsibilities

• Assist engineers with RTL review and simple modifications.
• Support Design-for-Test activities and run synthesis.
• Help maintain scripts and documentation.

Skills

Attention to detail

Basic understanding of digital logic

Willingness to learn ASIC design flows

Familiarity with Verilog or SystemVerilog

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Linux/Unix environments

Scripting (Python, Tcl, or Shell)

Job description

At SK Hynix Memory Solution, we’re at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting‑edge memory technologies are essential in today’s most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We’re looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you’ll be part of a team that’s pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We’re not just adapting to technological change – we’re driving it, with significant investments in artificial intelligence, machine learning, and eco‑friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what’s possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Key Responsibilities

• Assist engineers with basic RTL review, organization, and simple modifications (Verilog/SystemVerilog).
• Support Design-for-Test (DFT) activities such as scan chain checks, test structure integration, and report analysis.
• Help run synthesis and timing analysis flows using established scripts and tools.
• Review synthesis and static timing analysis (STA) reports to identify simple issues (e.g., setup/hold violations).
• Assist in debugging design and timing issues under guidance from senior engineers.
• Help maintain scripts, documentation, and design checklists.
• Collaborate with team members across design, verification, and physical design.

Required Qualifications

• Pursuing a Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of digital logic (gates, flip‑flops, timing concepts).
• Familiarity with Verilog or SystemVerilog from coursework (no advanced design experience required).
• Willingness to learn ASIC design flows, tools, and methodologies.
• Strong attention to detail and ability to follow structured workflows.

Preferred Qualifications

• Introductory exposure to DFT concepts (scan, basic test ideas) through coursework or projects.
• Basic understanding of timing concepts (setup/hold, clock signals).
• Familiarity with Linux/Unix environments.
• Exposure to scripting (Python, Tcl, or Shell) is a plus but not required.

What You’ll Gain

• Foundational understanding of ASIC design and test methodologies.
• Hands‑on experience running synthesis and timing flows.
• Exposure to DFT concepts used in production silicon.
• Mentorship and guidance from experienced engineers.
• Practical experience working in a collaborative hardware development environment.

Compensation

$35/hr – $45/hr