Sr. / Staff ASIC Digital Design Engineer

SK hynix memory solutions America Inc.; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) match

Onsite amenities

Job summary

SK hynix memory solutions America Inc. in San Jose is seeking an experienced ASIC Digital Design engineer with expertise in DFT, Synthesis, Power and Timing analysis to drive automated flows and sign-off across multiple teams toward tapeout milestones.

The role requires extended experience with Synopsys and Tessent tool suites, strong scripting in tcl/perl/python, and a track record of frontend and physical implementation collaboration.

Qualifications

• Extensive frontend EDA tool experience (PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, Tessent, Tetramax).
• Low-Power Design flow with UPF.
• Unix/Linux familiarity with scripting (tcl/perl/python).
• Strong attention to detail and structured workflows.
• Bachelor's in Engineering with 8+ years or Master's with 6+ years.

Responsibilities

• Lead top-level DFT planning and integration.
• Manage ATPG and ATE interface, bring-up and failure analysis.
• Drive test time reduction strategies.
• Lead Synthesis, Formality, Timing checks; guide RTL delivery.
• Develop chip and block constraints; collaborate with PNR and RTL teams on power intent.
• Troubleshoot Synthesis/Timing/DFT/Power issues and drive flow improvements.
• Maintain scripts, docs, IP DK, and SoC signoff checklists.

Skills

DFT

Synthesis

Timing analysis

Unix/Linux

tcl scripting

python scripting

Education

Bachelor's in Engineering

Master's in Engineering

Tools

PT

DC

Formality

Tessent

Tetramax

VCS

PrimePower

PrimeClosure

LEC

Job description

Overview

San Jose

About the Company:

At SK Hynix Memory Solution, we are at the forefront of semiconductor innovation, developing advanced memory solutions powering mobile devices, data centers, and IT infrastructure. As a global leader in DRAM and NAND flash technologies, we drive the evolution of memory technology and its impact on performance and user experience. We are committed to sustainability and investing in innovations in AI, machine learning, and eco-friendly practices.

Position Overview

We are looking for a highly motivated ASIC Digital Design engineer with expertise in DFT, Synthesis, Power, and Timing analysis to support our hardware engineering team. As a member of the ASIC implementation team, you will drive automated flows to streamline sign-off for multiple teams and ensure high-quality deliveries to achieve tapeout milestones.

Responsibilities

• Extensive experience with Synopsys tool suites and Siemens Tessent tool suite.
• Responsible for top-level DFT planning and integration.
• Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure analysis.
• Driving test time reduction strategies.
• Leading Synthesis, Formality, Timing checks, provide guidance, interface with RTL design team for quality RTL delivery.
• Full chip and block constraints development & STA; working independently with the PNR & RTL design team on physical implementation & power-intent requirements.
• Troubleshooting Synthesis / Timing / DFT / Power related issues, continuously driving flow improvements.
• Help maintain scripts, documentation, IP DK, and SoC signoff checklists.

Required Qualifications

• Demonstrate expertise in multiple tapeouts, extensive experience in frontend tools such as PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, etc.
• Low-Power Design flow with UPF.
• Familiarity with UNIX/Linux environments, tcl/perl/python/shell scripting; AI-assisted flow experience is a plus.
• Strong attention to detail and ability to follow structured workflows.
• Bachelors in Engineering and 8+ years of related experience, or Masters in Engineering and 6+ years of related experience.

Preferred Qualifications

• Direct experience taping out designs in advanced semiconductor technology nodes (e.g., 7nm, 5nm, or below).
• Familiarity with voltage drop analysis.
• Experience with ATE bring-up, failure analysis and yield improvement.
• Experience with CDC/RDC/Lint checks.
• Experience with floorplan / timing-driven placement / clock-tree synthesis / Xtalk analysis.

Compensation and Benefits

SK hynix memory solutions America Inc. offers a competitive compensation package complemented by a comprehensive benefits package including medical, dental, vision, life insurance, 401(k) match, onsite amenities, and opportunities for career growth. Salary is tailored based on location, job grade, knowledge, skills, and experience, with consideration for internal equity.