SoC RTL Design Engineer for High-Performance SSDs

SKHMS Corporation; San Jose (CA); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Life insurance

401(k) match

Onsite gym

Cafeteria

Job summary

SK hynix memory solutions America Inc. is seeking an accomplished RTL design engineer to join the System on Chip (SoC) Design Team in San Jose.

You will contribute across the design cycle, from micro-architecture and RTL coding to timing closure and tapeout readiness for high‑performance SSDs and AI storage solutions. You will collaborate with Design Verification, Silicon Validation and Firmware groups, focusing on Verilog/SystemVerilog RTL, AMBA/PCIe/NAND/DDR protocols, and scripting in Python.

Qualifications

• Education: BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog.
• Experience with industry standard interfaces and verification methodologies.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Skills

RTL design (Verilog/SystemVerilog)

Micro-architecture knowledge

Python scripting

Linux CLI

Communication skills

Team collaboration

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

AMBA

PCIe

NAND

DDR

Job description

SK hynix memory solutions America Inc. is seeking an accomplished RTL design engineer to join the System on Chip (SoC) Design Team in San Jose.

You will contribute across the design cycle, from micro-architecture and RTL coding to timing closure and tapeout readiness for high‑performance SSDs and AI storage solutions. You will collaborate with Design Verification, Silicon Validation and Firmware groups, focusing on Verilog/SystemVerilog RTL, AMBA/PCIe/NAND/DDR protocols, and scripting in Python.