ASIC Design Intern: RTL, DFT & Timing

SK hynix memory solutions America Inc.; San Jose (CA); On-site; USD 48,216 - 61,992; Part time

Job summary

SK hynix memory solutions America Inc. is seeking an intern focused on ASIC design. You will assist engineers with RTL review, DFT activities, and run synthesis and timing analysis. The ideal candidate is pursuing a degree in Electrical or Computer Engineering, with a solid foundation in digital logic.

This role provides hands-on experience in a collaborative environment, with a compensation rate of $35/hr – $45/hr and mentorship from experienced engineers.

Qualifications

• Pursuing a Bachelor’s degree in Electrical Engineering or similar.
• Basic understanding of digital logic and familiarity with Verilog/SystemVerilog.
• Strong attention to detail with structured workflows.

Responsibilities

• Assist engineers with RTL review and simple modifications.
• Support Design-for-Test activities and run synthesis.
• Help maintain scripts and documentation.

Skills

Attention to detail

Basic understanding of digital logic

Willingness to learn ASIC design flows

Familiarity with Verilog or SystemVerilog

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Linux/Unix environments

Scripting (Python, Tcl, or Shell)

Job description

SK hynix memory solutions America Inc. is seeking an intern focused on ASIC design. You will assist engineers with RTL review, DFT activities, and run synthesis and timing analysis. The ideal candidate is pursuing a degree in Electrical or Computer Engineering, with a solid foundation in digital logic.

This role provides hands-on experience in a collaborative environment, with a compensation rate of $35/hr – $45/hr and mentorship from experienced engineers.