Physical Design Engineer – Timing & PPA for AI Accelerators

Tenstorrent; United States; Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is looking for a Physical Design Engineer to manage timing for subsystems in an AI accelerator chip. Candidates will collaborate with RTL designers to optimize performance, power, and area (PPA) while incorporating innovative techniques. Required qualifications include a BS/MS/PhD in EE/ECE/CE/CS, proficiency with industry-standard design tools like Innovus, and a strong foundation in low-power design techniques. Compensation ranges from $100k to $500k based on experience and other factors.

Qualifications

• Experience in synthesis, placement and routing, and timing closure on taped-out designs.
• Deep understanding of advanced node challenges and low-power design techniques.
• Experience in driving physical design requirements from early architecture through final signoff.

Responsibilities

• Own timing for subsystems in an AI accelerator chip.
• Collaborate with RTL designers to assess buildability and PPA of micro-architectural features.
• Develop timing constraints and drive transition to physical design implementation.

Skills

SOC/ASIC physical design expertise

PPA optimization

Debugging complex issues

Strong collaboration skills

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

Innovus

PrimeTime

RedHawk

Tcl

Perl

Python

Job description

Tenstorrent is looking for a Physical Design Engineer to manage timing for subsystems in an AI accelerator chip. Candidates will collaborate with RTL designers to optimize performance, power, and area (PPA) while incorporating innovative techniques. Required qualifications include a BS/MS/PhD in EE/ECE/CE/CS, proficiency with industry-standard design tools like Innovus, and a strong foundation in low-power design techniques. Compensation ranges from $100k to $500k based on experience and other factors.