Top Level Physical Design Engineer

Tenstorrent; United States; Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is looking for a Physical Design Engineer to manage timing for subsystems in an AI accelerator chip. Candidates will collaborate with RTL designers to optimize performance, power, and area (PPA) while incorporating innovative techniques. Required qualifications include a BS/MS/PhD in EE/ECE/CE/CS, proficiency with industry-standard design tools like Innovus, and a strong foundation in low-power design techniques. Compensation ranges from $100k to $500k based on experience and other factors.

Qualifications

• Experience in synthesis, placement and routing, and timing closure on taped-out designs.
• Deep understanding of advanced node challenges and low-power design techniques.
• Experience in driving physical design requirements from early architecture through final signoff.

Responsibilities

• Own timing for subsystems in an AI accelerator chip.
• Collaborate with RTL designers to assess buildability and PPA of micro-architectural features.
• Develop timing constraints and drive transition to physical design implementation.

Skills

SOC/ASIC physical design expertise

PPA optimization

Debugging complex issues

Strong collaboration skills

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

Innovus

PrimeTime

RedHawk

Tcl

Perl

Python

Job description

Tenstorrent is leading the industry on cutting‑edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking a Physical Design Engineer to own timing for subsystems in an AI accelerator chip. You will collaborate with RTL designers during the exploration phase to assess buildability and PPA of micro-architectural features, develop timing constraints, and drive the transition to physical design implementation. Your responsibilities will include synthesis, place and route, timing analysis and closure, and power optimization. AI accelerators provide a wide design space, and you’ll play a key role in selecting micro‑architecture design points that meet die‑size and PPA goals.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands‑on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast‑paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped‑out designs.
• Expertise with industry‑standard tools (Innovus, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low‑power design techniques (power gating, multi‑Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting‑edge AI accelerators and high‑performance CPUs on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next‑generation chiplet architectures.
• End‑to‑end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high‑performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.