Hybrid Physical Design Engineer for AI Accelerator IP

Tenstorrent; United States; Hybride; USD 100 000 - 500 000; Plein temps

Résumé du poste

Tenstorrent is seeking a hands-on physical design engineer to own blocks end to end, from synthesis through PnR to GDSII signoff, influencing PPA and power budgets. This role requires collaboration with RTL, clocking, and IP teams across advanced nodes.

We offer hybrid roles based in Toronto, Austin, or Belgrade, with learning opportunities across RISC-V CPU and AI IP. Applicants at varying experience levels will be considered; offers align with level and market norms.

Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout.
• Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).
• Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC).
• Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).

Responsabilités

• Own blocks end to end from synthesis through PnR and GDSII signoff.
• Close critical paths and hit power budgets working with RTL owners.
• Provide IP integration collateral and signoff reports (LEF/DEF, timing/power models, GDS).
• Collaborate with architecture, RTL, and chiplet integration teams.

Connaissances

Block-level design

PPA-driven design

Signoff collaboration

Scripting (Tcl, Python, Perl)

Formation

BS/MS/PhD in EE/ECE/CE/CS

Outils

Innovus

ICC2/FusionCompiler

PrimeTime

Description du poste

Tenstorrent is seeking a hands-on physical design engineer to own blocks end to end, from synthesis through PnR to GDSII signoff, influencing PPA and power budgets. This role requires collaboration with RTL, clocking, and IP teams across advanced nodes.

We offer hybrid roles based in Toronto, Austin, or Belgrade, with learning opportunities across RISC-V CPU and AI IP. Applicants at varying experience levels will be considered; offers align with level and market norms.