Physical Design Engineer: PnR, PPA & Timing

Proxelera PVT LTD; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Proxelera PVT LTD is seeking a Physical Design Engineer with strong expertise in Place & Route (PnR), PPA optimization, and timing convergence for advanced technology nodes. You will drive block-level physical design from netlist to GDSII and collaborate with RTL/DFT/STA teams to ensure successful tapeouts.

The role requires experience in floorplanning, CTS, timing closure, EMIR analysis, and signoff methodologies.

Qualifications

• Experience in physical design and PnR flow.
• Ability to perform floorplanning, CTS, routing and signoff.
• Strong understanding of PPA optimization and timing closure techniques.
• Proficiency with timing constraints (SDC) and STA.
• Experience with EMIR analysis and IR drop.
• Collaboration with RTL/DFT/STA teams for tapeout.

Responsibilities

• Drive block-level physical design from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA).
• Achieve timing closure across corners and modes.
• Analyze and resolve setup/hold/transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure tapeout.
• Debug physical design issues and drive convergence within schedules.

Skills

Physical design

PnR flow

PPA optimization

Timing convergence

Floorplanning

CTS

Routing

STA

SDC

EMIR analysis

Cross-functional teams

Education

Bachelor's in Electrical Engineering

Master's preferred

Tools

Cadence Innovus

RedHawk

Voltus

Job description

Proxelera PVT LTD is seeking a Physical Design Engineer with strong expertise in Place & Route (PnR), PPA optimization, and timing convergence for advanced technology nodes. You will drive block-level physical design from netlist to GDSII and collaborate with RTL/DFT/STA teams to ensure successful tapeouts.

The role requires experience in floorplanning, CTS, timing closure, EMIR analysis, and signoff methodologies.