Senior Physical Design Engineer: PnR, PPA, Timing Closure

Wipro Technologies

Austin (TX)

On-site

USD 100,000 - 180,000

Full time

4 days ago

Be an early applicant

Application generator

Turn this role into an interview — a resume and cover letter built around what this employer wants.

Get past ATS filters

Benefits offered by this job

Full range of medical and dental\nbene

Disability insurance

Paid time off

Job summary

Wipro Limited in Austin, Texas is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence to drive block-level design from netlist to GDSII. You will perform floorplanning, CTS, routing, and timing closure across advanced nodes, collaborating with RTL/STA/Signoff teams to tape out complex silicon.

The role requires 8–10 years in VLSI physical design, expertise with Fusion Compiler/ICC2 and PrimeTime, and hands-on PPA and EMIR analysis.

Qualifications

8–10 years of experience in VLSI Physical Place and Route (PnR) and related signoff
Experience with 7nm/5nm/3nm nodes preferred
Strong debugging and problem-solving skills in physical design and PPA
Proficiency with industry-standard EDA tools listed in the job description

Responsibilities

Drive block-level physical design implementation from netlist to GDSII
Perform floorplanning, power planning, placement, CTS, routing, and physical verification
Optimize designs for Power, Performance, and Area (PPA) targets
Achieve timing closure across corners and modes
Analyze and resolve timing violations and EMIR-related issues
Develop and maintain timing constraints (SDC) and STA signoff methodologies
Collaborate with RTL, DFT, STA, and Signoff teams for tapeout
Debug physical design issues and drive design convergence within project schedules