Physical Design Lead/Manager

KP Construx; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

KP Construx is seeking a senior IC physical design engineer to lead complex partitioned implementations using RTL2GDS flow and cutting-edge processes (3nm+). You will drive design for testability, floorplanning, and place-and-route, ensuring robust low-power designs and optimized clocking.

Ideal candidates have 10+ years in physical design, experience with Cadence Innovus, clock-tree synthesis, UPF, and PTPX power flow, and can deliver on tight power and performance goals in a fast-paced

Qualifications

• 10+ years of experience in physical design.
• RTL2GDS flow and design tapeouts in 3nm or smaller process tech.
• Experience with Cadence tool: Innovus.
• Experience with custom or regular clock tree synthesis to reduce clock power.
• Experience with low-power implementation, power gating, multiple voltage rails, and UPF knowledge.
• Experience with PTPX power flow.

Responsibilities

• Handle physical design implementation for partitions using advanced techniques.
• Resolve design and flow issues related to physical design; identify solutions and execute them.

Skills

RTL2GDS flow

3nm tapeouts

Innovus Cadence

Clock tree synthesis

Low-power design

Power gating

Multiple voltage rails

UPF knowledge

PTPX power flow

Tools

Innovus Cadence

Job description

• They'll handle the physical design implementation for various partitions using advanced tech, including things like physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, and EMIR.
• They'll also sort out any design and flow issues related to physical design, figure out solutions, and get things done.

Required Skills:

• 10+ years of experience in physical design.
• A good grasp of RTL2GDS flow and design tapeouts in 3nm or smaller process tech.
• Experience wit h Cadence tool: Innovus
• Experience with custom or regular clock tree synthesis (block or top level) and techniques to reduce clock power.
• Experience with low-power implementation, power gating, multiple voltage rails, and UPF knowledge.
• Experience with PTPX power flow.
• rails, and UPF knowledge. Experience with PTPX power flow.