Physical Design Engineer Intern: Synthesis & Timing

Jobtailor; California (MO); On-site; USD 60,000 - 80,000; Full time

Job summary

Jobtailor is seeking a Master's student in Electrical/Computer Engineering to contribute to advanced digital design flows. You will perform synthesis, floor planning, place-and-route, clock insertion, and timing analysis on complex blocks using leading EDA tools.

You will also script in Python, TCL, Perl, and Shell to streamline design activities. The role requires coursework in VLSI, digital logic, and related areas, with experience in Unix environments and exposure to PrimeTime, Cadence

Qualifications

• Currently enrolled in a Master’s Degree in Electrical Engineering, Computer Engineering, or a related field.
• Expected graduation date between Fall 2027 and Summer 2028.
• Completed coursework in VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics.
• Proficiency in Python, TCL, Perl, and Shell.
• Experience working in a Unix-type environment.
• Experience using Synopsys PrimeTime, Cadence Tempus, and Mentor tools.
• Strong analysis, problem-solving, and communication skills.
• Must be eligible to access export-controlled information under U.S. law; applicants may be subject to export license review

Responsibilities

• Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry-standard EDA tools
• Write Python, TCL, Perl, and Shell scripts to support design and development activities
• Analyze, debug, and implement fixes for design violations using CAD tools
• Collaborate with RTL, synthesis, and other design teams to resolve congestion and timing bottlenecks
• Ensure designs converge and integrate in a timely manner

Skills

Analysis

Problem-Solving

Communication

Education

Master's Degree in ECE or related

Tools

Synthesis

Floor Planning

Place And Route

Clock Insertion

Timing Analysis

Python Programming

TCL Programming

Perl Programming

Shell Scripting

Static Timing Analysis

Job description

Jobtailor is seeking a Master's student in Electrical/Computer Engineering to contribute to advanced digital design flows. You will perform synthesis, floor planning, place-and-route, clock insertion, and timing analysis on complex blocks using leading EDA tools.

You will also script in Python, TCL, Perl, and Shell to streamline design activities. The role requires coursework in VLSI, digital logic, and related areas, with experience in Unix environments and exposure to PrimeTime, Cadence