Silicon Design Engineer

Jobtailor; San Jose (CA); On-site; USD 170,000 - 210,000; Full time

Job summary

Jobtailor in San Jose seeks an experienced RTL-to-PD engineer to drive design realization from RTL to tapeout. You will optimize synthesis, timing, and physical layout while coordinating with frontend and backend teams.

You will write timing constraints, run static timing analysis, and implement power-aware flows, leveraging Cadence and Synopsys toolchains and AI-assisted automation to accelerate iterations.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related technical discipline
• 3+ years of hands-on RTL-to-PD implementation experience
• Demonstrated success taking designs from synthesis through tapeout on real silicon
• Proficiency in SystemVerilog/Verilog
• Deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains
• Familiarity with associated quality and sign-off checks
• Strong command of static timing analysis
• Ability to write timing constraints from scratch based on RTL-level design understanding
• Experience developing and maintaining scripted, automated design flows
• Exposure to AI-assisted automation tools is a strong plus

Responsibilities

• Own RTL-to-PD handoff flows to PD partners, including synthesis, timing constraints, UPF, and static checks
• Ensure designs meet quality, performance, power, and area targets
• Drive timing closure by authoring precise timing constraints from RTL understanding
• Run static timing analysis and resolve setup violations across complex multi-corner environments
• Execute floorplanning and physical implementation using Cadence/Synopsys tools
• Make informed macro-placement and tool-option decisions to optimize PPA
• Build and maintain scripted, automated design flows for synthesis, analysis, and sign-off
• Leverage AI agents and modern automation tools to accelerate iteration and reduce manual overhead
• Collaborate with RTL design, DFT, and verification teams on frontend-to-backend handoffs
• Enforce quality checks and ensure seamless integration across the design hierarchy
• Contribute to post-DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration

Skills

RTL-to-PD Implementation

Static Timing Analysis

SystemVerilog/Verilog Proficiency

Cadence/Synopsys Toolchain Familiarity

Automated Design Flows Development

Timing Constraints Authoring

Synthesis

Physical Design

Power Analysis

Formal Verification

DFT Scan Integration

Macro-Placement Optimization

Multi-Corner Environment Analysis

AI Tools Familiarity

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline

Tools

Cadence Tools

Synopsys Tools

AI Automation Tools

Scripting for Automation

Job description

• Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, UPF, and static checks
• Ensure designs meet quality, performance, power, and area targets
• Drive timing closure by authoring precise timing constraints from RTL understanding
• Run static timing analysis and resolve setup violations across complex multi-corner environments
• Execute floorplanning and physical implementation using Cadence/Synopsys tools
• Make informed macro-placement and tool-option decisions to optimize PPA
• Build and maintain scripted, automated design flows for synthesis, analysis, and sign-off
• Leverage AI agents and modern automation tools to accelerate iteration and reduce manual overhead
• Collaborate with RTL design, DFT, and verification teams on frontend-to-backend handoffs
• Enforce quality checks and ensure seamless integration across the design hierarchy
• Contribute to post-DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline
• 3+ years of hands-on RTL-to-PD implementation experience
• Demonstrated success taking designs from synthesis through tapeout on real silicon
• Proficiency in SystemVerilog/Verilog
• Deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains
• Familiarity with associated quality and sign-off checks
• Strong command of static timing analysis
• Ability to write timing constraints from scratch based on RTL-level design understanding
• Experience developing and maintaining scripted, automated design flows
• Exposure to AI-assisted automation tools is a strong plus
• Demonstrated fluency with modern AI tools and workflows, such as AI assistants for research, analysis, or productivity

Core Competencies

Expertise in RTL-to-PD implementation, including synthesis, timing analysis, and physical design, with a strong focus on quality, performance, power, and area optimization. Proficient in developing automated design flows and leveraging AI tools to enhance efficiency and accuracy in design processes.

Highest-signal resume keywords

• RTL-to-PD Implementation
• Static Timing Analysis
• SystemVerilog/Verilog Proficiency
• Cadence/Synopsys Toolchain Familiarity
• Automated Design Flows Development

ATS Optimization Keywords

Hard Skills

• RTL-to-PD Implementation
• Static Timing Analysis
• Timing Constraints Authoring
• Synthesis
• Physical Design
• Power Analysis
• Formal Verification
• DFT Scan Integration
• Macro-Placement Optimization
• Multi-Corner Environment Analysis

Industry Keywords

• Electrical Engineering
• Computer Engineering
• Design Verification
• Quality Checks
• Tapeout Process
• UPF Creation
• CDC/RDC Checks
• Design Hierarchy Integration

Tools & Technologies

• Cadence Tools
• Synopsys Tools
• AI Automation Tools
• Scripting for Automation