Physical Design Engineer

AMC OU Ambarella Corp; United States; On-site; USD 140,000 - 156,000; Full time

Benefits offered by this job

New-hire RSU grants

Annual RSU grants

Highly competitive benefits

Job summary

AMC OU Ambarella Corp is seeking a Physical Design Engineer to join their team in the United States. In this role, you will be responsible for all aspects of physical design implementation for low power AI SoC, including floor-planning and static timing analysis.

Candidates should possess a BS/MS in EE or computer science, with 3–5+ years of experience and a strong background in VLSI design. The position offers a competitive salary range of $140,000–$156,000 along with various benefits and the potential for full-time employment.

Qualifications

• 3–5+ years of experience.
• Proficient in programming and scripting skills.
• Solid understanding of hierarchical physical design strategies.

Responsibilities

• Perform floor-planning and auto place and route.
• Conduct static timing analysis and eco implementation.
• Ensure physical layout verification at block and/or full chip level.

Skills

VLSI digital design

Layout and timing closure

Programming (Perl, Python, TCL)

Hardware design languages (Verilog, VHDL)

Education

BS/MS in EE/computer science or equivalent

Tools

Cadence Innovus

Synopsys Fusion Compiler

Mentor Calibre

Job description

Job Description

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII. The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor‑planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.

Responsibilities

• Floor‑planning
• Auto place and route
• Static timing analysis
• Eco implementation
• Signal integrity analysis
• EM/IR analysis
• Formal verification
• Physical layout verification (LVS/DRC/DFM) at block and/or full chip level

Requirements

• BS/MS in EE/computer science or equivalent experience
• 3–5+ years of experience
• Good understanding in VLSI digital design, layout, and timing closure
• Basic knowledge of circuit design, device delays, and timing at gate‑level
• Familiarity with industry EDA tools such as Cadence Innovus, Quantus, Tempus, Synopsys Fusion Compiler, ICC2, StarRC, Primetime, and Mentor Calibre
• Proficient programming and scripting skills (Perl, Python, TCL, C‑shell, make)
• Hardware design languages such as Verilog and VHDL
• Self‑motivated team worker with strong verbal and written interpersonal skills
• Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC is an added advantage
• Solid understanding of hierarchical physical design strategies, methodologies, and nanometer advanced node technology issues
• Hands‑on experience in STA including multi‑mode, multi‑corner analysis and ability to analyze and fix critical timing issues
• Proven track record of delivering tape‑out quality GDSII with silicon success in sub 10nm is a plus

The base salary range is $140,000–$156,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full‑time regular position. We also offer new‑hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.

Combining technical expertise and a commitment to quality, Ambarella has established itself as the industry standard for excellence in video performance by offering pristine imagery, efficient compression, and low‑power operation.

For our next phase of growth, we are looking for talented team members to help us deliver our advanced computer vision algorithms to tomorrow’s intelligent video products. Our target applications include autonomous vehicles, intelligent video surveillance, self‑flying drones, smart wearable cameras, 360‑degree immersive video, and more.