ASIC Design Engineer Intern

Ambarella; Washington (District of Columbia); On-site; USD 120,000 - 150,000; Full time

Job summary

Ambarella is seeking a skilled ASIC/RTL engineer to design video processing cores and neural network accelerators for edge devices. You will implement Verilog/SystemVerilog, synthesize RTL, and optimize timing, area and power.

You will develop test benches and verification plans using SystemVerilog, UVM, C++, and Perl, participate in chip bring-up, and collaborate on computer vision algorithms for autonomous vehicles and intelligent cameras.

Qualifications

• Master’s degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.
• Strong understanding of computer architecture, logic design and VLSI design.
• Knowledge of SystemVerilog, Verilog, and Perl.
• Knowledge of design verification, and functional coverage.
• Ability to program scripting languages and the ability to write assembly language programs.
• Strong communication skills and a good team player.

Responsibilities

• Design and implement video compression logic, image processing logic, vector processing and neural network accelerator logics, and processor cores, in Verilog and SystemVerilog.
• Synthesize and optimize RTL for timing, area and power.
• Develop unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using SystemVerilog, UVM, C++, and Perl scripts.
• Develop test plans, random and directed test cases, perform logic verification and functional coverage analysis.
• Develop front-end methodologies and tool flows and participate in chip bring-up and testing.

Skills

Verilog

SystemVerilog

C++

Perl

UVM

Team communication

Education

Master’s degree in Electrical/Electronics/Computer Engineering

Tools

Verilog

SystemVerilog

UVM

Job description

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Position Responsibilities: Designing and implementing video compression logic, image processing logic, vector processing and neural network accelerator logics, and processor cores, in Verilog and System Verilog. Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. Synthesize and optimize RTL for timing, area and power. Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using System Verilog, UVM, C++, and Perl scripts. Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis. Developing front-end methodologies and tool flows. Participating in chip bring-up and testing.

Requirements

Master’s degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience. Good understanding of computer architecture, logic design and VLSI design. Knowledge of System Verilog, Verilog, and Perl. Knowledge of design verification, and functional coverage. Ability to program scripting languages and the ability to write assembly language programs. Strong communication skills and a good team player. Knowledge of logic synthesis and timing closer Combining technical expertise and a commitment to quality, Ambarella has established itself as the industry standard for excellence in video performance by offering pristine imagery, efficient compression, and low-power operation. For our next phase of growth, we are looking for talented team members to help us deliver our advanced computer vision algorithms to tomorrow’s intelligent video products. Our target applications include autonomous vehicles, intelligent video surveillance, self-flying drones, smart wearable cameras, 360-degree immersive video, and more.