Staff ASIC Design Engineer

AMC OU Ambarella Corp; United States; On-site; USD 195,000 - 226,000; Full time

Benefits offered by this job

Competitive benefits

Annual RSU grants

New-hire RSU grants

Job summary

AMC OU Ambarella Corp is seeking an experienced engineer specializing in video compression and image processing. The successful candidate will leverage their expertise in System Verilog to design and implement systems for advanced AI applications across various sectors.

With a competitive salary range of $195,000–$226,000, this position offers exciting opportunities to work on the forefront of computer vision technology that powers autonomous vehicles, smart cameras, and more.

Qualifications

• 5–10 years of experience in related fields.
• Good understanding of computer architecture and logic design.
• Knowledge of design verification and functional coverage.
• Ability to program in scripting languages and write assembly language.

Responsibilities

• Design and implement video compression and image processing systems.
• Logic design, implementation, and verification using Verilog and System Verilog.
• Synthesize and optimize RTL for timing and power.
• Develop front-end methodologies and participate in chip bring-up.
• Analyze code coverage and provide verification recommendations.

Skills

System Verilog

Verilog

Python

Perl

Logic design

VLSI design

Scripting languages

Communication skills

Education

Master’s degree in Electrical, Electronics, or Computer Engineering

Job description

Overview

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Ambarella is a leading fabless semiconductor company at the forefront of edge AI-based computer vision. Our SoCs (System-on-Chips) power everything from autonomous driving and ADAS to intelligent video security and robotics. We are building the next generation of Edge AI, operating at the intersection of high-performance hardware and real-world software deployment.

Responsibilities

• Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and LLM inference—alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems.
• Logic design, implementation, and verification using Verilog, System Verilog, and any required programming and scripting languages.
• Synthesize and optimize RTL for timing, area, and power.
• Explore micro-architecture and architectural tradeoffs via quick modeling using scripting languages such as Python or Perl.
• Develop front-end methodologies and tool flows.
• Participate in chip bring-up and testing.
• Analyze and review code coverage and functional coverage and provide recommendations to the verification team to address any gaps.

Requirements

• Master’s degree in Electrical, Electronics, or Computer Engineering with 5–10 years of experience.
• Good understanding of computer architecture, logic design, and VLSI design.
• Knowledge of System Verilog, Verilog, Python, and Perl.
• Knowledge of design verification and functional coverage.
• Ability to program in scripting languages and write assembly language programs.
• Strong communication skills, a good team player, and adept problem-solving abilities.
• Knowledge of logic synthesis and timing closure is a plus.

Compensation & Benefits

The base salary range is $195,000–$226,000, with additional new-hire RSU grants, annual RSU grants, and other competitive benefits. Compensation is determined based on location, experience, and peer pay.

Target Applications

We are looking for talented team members to help us deliver advanced computer vision algorithms to tomorrow’s intelligent video products, including autonomous vehicles, intelligent video surveillance, self-flying drones, smart wearable cameras, 360-degree immersive video, and more.