Physical Design Engineer

Thundersoft; Austin (TX); On-site; USD 160,000 - 210,000; Full time

Job summary

Thundersoft in Texas is seeking experienced Physical Design Engineers across multiple levels to contribute to ASIC implementation and tapeout-ready flows. You will work with architecture, RTL, DFT, CAD and product teams to deliver high-performance, low-power SoCs and IP blocks through floorplanning, PnR, CTS, timing, and signoff.

The role offers exposure to advanced design techniques and leadership opportunities, with career progression from Engineer to Principal Engineer as you demonstrate

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 4+ years in ASIC design or related work.
• Master's degree in Science, Engineering, or related field with 3+ years in ASIC design or related work.
• PhD in Science, Engineering, or related field with 2+ years in ASIC design or related work.
• 8+ years industry experience and lead physical design execution for large subsystems.

Responsibilities

• Floorplanning, power planning, place and route, clock tree synthesis, timing closure.
• Signal integrity analysis and physical verification.
• ECO implementation and design signoff activities.
• Drive cross-functional alignment among Design, DFT, CAD, Verification, and Product Engineering teams.

Skills

Physical design leadership

Cross-functional alignment

Automation solutions

Signal integrity

Debugging skills

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Job description

We are seeking highly motivated Physical Design Engineers across multiple career levels to

join our growing ASIC implementation team. In this role, you will contribute to the

development and execution of advanced physical design methodologies for complex, high

performance, low-power SoCs and IP blocks.

You will work closely with architecture, RTL, DFT, verification, CAD, and product

engineering teams to implement and deliver industry leading designs from synthesis

through final tapeout.

The ideal candidate possesses strong technical expertise in physical implementation,

Depending on experience and demonstrated technical leadership, candidates may be

considered for Engineer, Senior Engineer, Staff Engineer, or Principal Engineer

Physical Design responsibilities include floorplanning, power planning, place and route,

clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO

implementation, and design signoff activities.

The role supports Qualcomm's advanced SoC and core design programs across GPU,

Multimedia, AI, Compute, Connectivity, Modem, DDR, Audio, and other next-generation

technologies.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• 8+ years industry experience
• Lead physical design execution for large subsystems or critical SoC partitions.
• Define implementation strategies to achieve aggressive power, performance, area, and
• Drive cross-functional technical alignment among Design, DFT, CAD, Verification, and Product Engineering teams.
• Develop scalable methodologies, flow improvements, and automation solutions adopted across projects.
• Act as a technical subject matter expert in advanced physical implementation and design closure.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and relevant experience in ASIC design, implementation, verification, validation, integration, or related engineering disciplines.
• Experience with digital ASIC physical implementation methodologies.
• Understanding of power, performance, area, timing, and physical design tradeoffs.
• Experience working in Linux/Unix environments.
• Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages.
• Strong analytical, problem-solving, and debugging skills.

Preferred Qualifications

• Experience with complete Physical Design Flow from synthesis through tapeout.
• Physical design expertise including floorplanning, power planning, placement, CTS, routing, timing optimization, and closure
• Experience using Cadence Innovus and/or Synopsys Fusion Compiler.
• Static Timing Analysis and timing closure experience using Synopsys PrimeTime.
• Knowledge of MMMC implementation methodologies and advanced-node design closure.
• Experience with DFT-aware implementation and functional timing constraints.
• Experience with RC extraction, signal integrity analysis, cross-talk analysis, ECO implementation, and formal verification.
• Experience with low-power implementation techniques, UPF methodologies, and power domain analysis.
• Strong communication, collaboration, and technical leadership capabilities.

Technical Expertise Areas Successful candidates may possess expertise in one or