Physical Design Engineer

Zodiac Solutions, Inc; California; On-site; USD 140,000 - 190,000; Full time

Job summary

Zodiac Solutions, Inc. seeks an experienced ASIC/SoC Physical Design Engineer in California to own the end-to-end flow from RTL to tape-out.

You will lead synthesis, STA, timing closure, and P&R, with hands-on CTS and CTS optimization and close collaboration with IC Design teams. The role emphasizes floorplanning, physical verification, EM/IR analysis, and scripting with TCL/PERL to improve flow efficiency.

Qualifications

• Experience with Cadence Innovus and full physical design flow from RTL to tape-out.
• Hands-on synthesis, STA, timing closure, P&R, CTS, floorplanning, and physical verification.
• EM/IR analysis and scripting in TCL/PERL.
• Proficiency with industry-standard EDA tools and strong communication.

Responsibilities

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• Setup and synthesize RTL designs.
• Perform timing closure using various methodologies, including top-level STA.
• Conduct EM/IR analysis.
• Execute Place & Route (P&R).
• Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.
• Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.
• Contribute to flow and methodology development.
• Collaborate closely with IC Design and RTL Engineering teams.

Skills

RTL to Tape-out

Synthesis

STA

Timing Closure

Place & Route

CTS

Floorplanning

Physical Verification

EM/IR Analysis

TCL scripting

PERL scripting

EDA Tools

Communication

Education

Bachelor's in Electrical/Electronics Engineering

Tools

Cadence Innovus

Job description

Key Responsibilities

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.


• Setup and synthesize RTL designs.


• Perform timing closure using various methodologies and strategies, including top-level STA.


• Conduct EM/IR analysis.


• Execute Place & Route (P&R).


• Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.


• Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.


• Contribute to flow and methodology development.


• Collaborate closely with IC Design and RTL Engineering teams.

Required Skills

• Strong experience with Cadence Innovus.


• Expertise in the complete Physical Design cycle from RTL to Tape-out.


• Hands-on experience in:


• Synthesis


• Static Timing Analysis (STA)


• Timing Closure


• Place & Route


• Clock Tree Synthesis (CTS)


• Floorplanning


• Physical Verification


• EM/IR Analysis


• Strong TCL and/or PERL scripting skills.


• Proficiency with industry-standard EDA tools.


• Excellent communication and collaboration skills.

Education

• Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.

Preferred Profile

• Deep expertise in top-level floorplanning and STA.


• Proven success delivering complex ASIC/SoC designs through tape-out.