Physical Design Engineer

ACCLiiVE; San Jose (CA); Presencial; USD 140.000 - 220.000; Jornada completa

Descripción de la vacante

Accliive is seeking a senior engineer in the United States (California, San Jose) to lead end-to-end Physical Design. You will drive synthesis, physical verification, timing closure, CTS optimization, P&R, and floorplanning while collaborating closely with IC Design and RTL teams.

The role emphasizes strong Cadence Innovus experience, complete PD cycle mastery, and hands-on scripting with TCL or PERL.

Formación

• Strong experience with end-to-end Physical Design flow from RTL to tape-out.
• Hands-on in: Synthesis, STA, Timing Closure, Place & Route, CTS, Floorplanning, Physical Verification, EM/IR analysis.

Responsabilidades

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• Setup and synthesize RTL designs.
• Perform timing closure using various methodologies and strategies, including top-level STA.
• Conduct EM/IR analysis.
• Execute Place & Route (P&R).
• Develop and optimize Clock Tree Synthesis (CTS).
• Perform floorplanning and layout activities with top-level expertise.
• Collaborate with IC Design and RTL Engineering teams.

Conocimientos

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Educación

Bachelor's Degree in Electrical Engineering

Herramientas

Cadence Innovus

Descripción del empleo

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.


• Setup and synthesize RTL designs.


• Perform timing closure using various methodologies and strategies, including top-level STA.


• Conduct EM/IR analysis.


• Execute Place & Route (P&R).


• Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.


• Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.


• Contribute to flow and methodology development.


• Collaborate closely with IC Design and RTL Engineering teams.

Key Responsibilities

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.


• Setup and synthesize RTL designs.


• Perform timing closure using various methodologies and strategies, including top-level STA.


• Conduct EM/IR analysis.


• Execute Place & Route (P&R).


• Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.


• Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.


• Contribute to flow and methodology development.


• Collaborate closely with IC Design and RTL Engineering teams.

Required Skills

• Strong experience with Cadence Innovus.


• Expertise in the complete Physical Design cycle from RTL to Tape-out.


• Hands-on experience in:
  
  
  
  • Synthesis
  
  
  • Static Timing Analysis (STA)
  
  
  • Timing Closure
  
  
  • Place & Route
  
  
  • Clock Tree Synthesis (CTS)
  
  
  • Floorplanning
  
  
  • Physical Verification
  
  
  • EM/IR Analysis
  
  
  
  


• Strong TCL and/or PERL scripting skills.


• Proficiency with industry-standard EDA tools.


• Excellent communication and collaboration skills.

Education

• Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.

Preferred Profile

• Deep expertise in top-level floorplanning and STA.


• Proven success delivering complex ASIC/SoC designs through tape-out.

Accliive, is an Engineering and IT Talent Services company working with Fortune 500 clients and is based out of Boston, MA. Accliive works extensively in all the major industries like Manufacturing, Semiconductor, Aerospace, BFSI, Oil and Gas, Utilities, Healthcare and many more. Acclive is focused on providing customer centric solutions and career centric solutions.