Datacenter Compute SoC Performance Modeling Architect

MediaTek Research Lab Inc.; San Jose (CA); On-site; USD 211,000 - 356,000; Full time

Benefits offered by this job

Performance bonus

Health insurance

Life and disability insurance

401K retirement plan

Paid holidays

Vacation time

Parental leave

Job summary

MediaTek Research Lab Inc. is seeking a Datacenter Compute SoC Performance Modeling Architect to define our next-generation cloud processors.

You will develop cycle-accurate simulators and evaluate design trade-offs across cores, memory subsystems, and interconnects for datacenter workloads. The role requires 5+ years in performance modeling, strong C++ and Python skills, and deep knowledge of modern CPU microarchitecture.

Qualifications

• Education: Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• Experience: 5+ years in CPU, compute core, SoC, or system-level performance modeling and architectural analysis.
• Datacenter focus: experience profiling hyperscaler workloads (SPEC CPU, cloud microservices, big data analytics).
• Proficiency in modern C++ (C++14/17+) and OO design.
• Strong Python or Perl for data analysis and automation.
• Knowledge of memory hierarchies, MESI/MOESI, DDR/LPDDR5/6, HBM, PCIe/CXL, AMBA CHI/AXI, UCIe.

Responsibilities

• Design, develop, and maintain cycle-accurate and TCL performance models for multi-core datacenter SoCs.
• Analyze workloads to drive architectural requirements and identify bottlenecks.
• Explore design trade-offs to optimize cache, memory bandwidth, latency, and interconnect topologies.
• Correlate models with RTL simulations, emulators, and silicon validation.
• Build tracing tools and dashboards; run automated performance regression pipelines.

Skills

C++ (modern)

Python scripting

CPU microarchitecture

Performance modeling

System-level modeling

Data center workloads

Education

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science

Tools

gem5

Sniper

Job description

Datacenter Compute SoC Performance Modeling Architect

Category

Algorithm & Architecture

Location

San Jose, CA

Experience

More than 4 Years Work Expe.

Job Description

MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you.Role SummaryWe are looking for a highly skilled Datacenter Compute SoC Performance Modeling Engineer. In this role, you will be at the foreground of defining our next-generation cloud and datacenter processors. You will develop and maintain high-speed, cycle-accurate, and transaction-level architectural simulators to evaluate design trade-offs, identify performance bottlenecks, and project system performance across a wide range of datacenter workloads.You will collaborate closely with CPU/Compute core architects, SoC architects, IP architects, workload characterization teams, and RTL designers to ensure our silicon delivers industry-leading performance-per-watt and scales efficiently to meet the demands of modern hyper-scale infrastructure.

Key Responsibilities

• Simulator Development: Design, develop, and maintain cycle-accurate and transaction-level performance models (C++/SystemC) for multi-core datacenter SoCs, including CPU cores, memory subsystems, interconnects (NoC), and high-speed I/O (PCIe/CXL).
• Workload Analysis & Profiling: Analyze and characterize cloud-native workloads, microservices, databases, and AI/ML data processing pipelines to drive architectural requirements.
• Performance Exploration: Conduct what-if analyses and architectural design sweeps to optimize cache sizes, memory bandwidth, latency, interconnect topologies, and core counts.
• Bottleneck Identification: Identify micro-architectural and system-level performance bottlenecks and propose innovative hardware or software solutions.
• RTL & Silicon Correlation: Work with RTL verification and post-silicon validation teams to correlate the performance model against RTL simulations, emulators, and actual silicon, ensuring model accuracy.
• Tooling & Infrastructure: Build and enhance tracing tools, data visualization dashboards, and automated performance regression pipelines using Python and data analysis libraries.

Location: open to San Jose, San Diego, Portland and Austin#LI-WC2

Main Requirements and Qualifications

• Qualifications
• Education: Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• Experience: 5+ years of industry experience in CPU, compute core, SoC, or system-level performance modeling and architectural analysis.
• Datacenter Focus: Experience profiling and analyzing hyperscaler workloads (e.g., SPEC CPU, cloud microservices, big data analytics, virtualization).
• Expert-level proficiency in modern C++ (C++14/17 or later) and object-oriented design.
• Strong scripting skills in Python or Perl for data analysis and automation.
• Deep understanding of high-performance CPU microarchitecture (out-of-order execution, branch prediction, etc.) or computation engines (like PE array, Graph based compute, …)
• Comprehensive knowledge of memory hierarchies, cache coherency protocols (e.g., MESI, MOESI), and main memory technologies (DDR & LPDDR5/6, HBM).
• Familiarity with on-chip interconnects (e.g., AMBA CHI, AXI), I/O protocols (PCIe/CXL) and multiple-die architecture (e.g., UCIe)
• Modeling Frameworks: Hands-on experience with industry-standard simulators (e.g., gem5, Sniper) or building proprietary trace-driven/execution-driven simulators from scratch.
• Communication: Ability to clearly present complex performance data and architectural trade-offs to cross-functional teams and leadership.
• Salary range: $211,000- $356,000
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.

MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.