Performance Modeling Engineer for AI ASICs

Normal Computing Corp.; Mountain View (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Normal Computing is an applied AI company building next- generation hardware and software for AI inference, with a growing team in Mountain View. We seek a Performance Modeling Engineer to craft a cycle-accurate TLM that sits between RTL and our broader modeling stack, ensuring accurate, production-ready parameterization for AI workloads.

You will collaborate with architecture, hardware design, and DV teams, validating models against RTL, FPGA prototypes, and synthesis results.

Qualifications

• 5+ years of performance modeling experience in a major semiconductor company.
• Ability to translate architectures into performant modeling code.
• Experience with multiple modeling techniques and languages.
• Excellent written and spoken communication skills.

Responsibilities

• Build and maintain a cycle-accurate approximate TLM of compute tiles, memory hierarchy, and interconnect in SystemC, C++, or Python.
• Translate TLM/RTL results with design data into calibrated latency, bandwidth, and energy parameters for end-to-end predictions.
• Provide the TLM as a reference golden model for DV, including scoreboards and performance checks, aligning RTL and TLM.
• Plan modeling work against the hardware roadmap and run sensitivity analyses to guide architecture and hardware decisions.

Skills

Performance modeling

Architecture understanding

Modeling languages

Communication skills

SystemC/C++/Python

Tools

AccelForge

Timeloop/Accelergy

CACTI

McPAT

gem5

Job description

Normal Computing is an applied AI company building next- generation hardware and software for AI inference, with a growing team in Mountain View. We seek a Performance Modeling Engineer to craft a cycle-accurate TLM that sits between RTL and our broader modeling stack, ensuring accurate, production-ready parameterization for AI workloads.

You will collaborate with architecture, hardware design, and DV teams, validating models against RTL, FPGA prototypes, and synthesis results.