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Normal Computing is seeking a Performance Modeling Engineer to build and maintain cycle-accurate TLMs for AI accelerator hardware. You will translate RTL, FPGA prototypes and synthesis results into calibrated latency, bandwidth, and energy parameters used by architecture and DV teams.
You will own the path from RTL to performance results, validate models against real workloads, and plan modeling work against the hardware roadmap, delivering actionable guidance to the team.
Normal Computing is seeking a Performance Modeling Engineer to build and maintain cycle-accurate TLMs for AI accelerator hardware. You will translate RTL, FPGA prototypes and synthesis results into calibrated latency, bandwidth, and energy parameters used by architecture and DV teams.
You will own the path from RTL to performance results, validate models against real workloads, and plan modeling work against the hardware roadmap, delivering actionable guidance to the team.