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Cspeed IO is seeking a PCB Design & Validation Engineer to own schematic capture and layout for test/eval boards and transceiver modules. The role spans validation across SerDes, data pipelines, and optical subsystems, with emphasis on high-speed NRZ routing and PDN design.
The engineer will develop validation plans, run measurements (eye diagrams, jitter, BER), and create automation in Python to streamline testing and data analysis. A BS/MS in EE is required, with 5+ years in relevant work.
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
We are seeking a PCB Design & Validation Engineer to own the design of test/eval boards and lead validation of our high-speed optical transceivers. You will design the PCB platforms that enable development and characterization, with the opportunity to lead PCB design for the transceiver module itself. You will review transceiver requirements, develop validation plans, and execute them across all major subsystems: Ethernet SerDes, internal data pipeline, laser/modulator, mux/demux, and the MCU controller with EEPROM and I2C interfaces.