Lead High-Speed PCB Design & Validation for Optical Transceivers

CScale; Palo Alto, Northern (CA, KY); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Cspeed IO is seeking a PCB Design & Validation Engineer to own schematic capture and layout for test/eval boards and transceiver modules. The role spans validation across SerDes, data pipelines, and optical subsystems, with emphasis on high-speed NRZ routing and PDN design.

The engineer will develop validation plans, run measurements (eye diagrams, jitter, BER), and create automation in Python to streamline testing and data analysis. A BS/MS in EE is required, with 5+ years in relevant work.

Qualifications

• BS/MS in Electrical Engineering or equivalent.
• 5+ years in PCB design and hardware validation.
• Experience with high-speed NRZ/SerDes preferred.

Responsibilities

• Own schematic capture, layout for test/eval boards and transceiver PCBs.
• Develop validation plans and execute silicon/module/system tests.
• Characterize SerDes jitter, eye diagrams, BER, and data throughput.
• Build test setups and Python automation; document procedures and results.

Skills

PCB design

High-speed validation

Python scripting

Lab instrumentation

I2C/SPI/serial

Education

BS/MS in Electrical Engineering or equivalent

Tools

Altium Designer

Cadence Allegro

VNA

TDR

Job description

Cspeed IO is seeking a PCB Design & Validation Engineer to own schematic capture and layout for test/eval boards and transceiver modules. The role spans validation across SerDes, data pipelines, and optical subsystems, with emphasis on high-speed NRZ routing and PDN design.

The engineer will develop validation plans, run measurements (eye diagrams, jitter, BER), and create automation in Python to streamline testing and data analysis. A BS/MS in EE is required, with 5+ years in relevant work.