Packaging Design Engineer – High‑Speed FPGA Packages

Advanced Micro Devices

San Jose (CA)

On-site

USD 120,000 - 170,000

Full time

14 days+
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Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices in San Jose, CA is seeking an experienced package design engineer within the AMD Adaptive and Embedded Computing Group. You will work across chip, technology and systems teams to define cost-effective, high-performance packaging solutions and support from design start to sign-off.

The ideal candidate has hands-on Cadence packaging experience, strong understanding of high-speed signaling and power integrity, and the ability to collaborate across design centers to deliver

Qualifications

  • Bachelor’s or Master’s degree in Engineering.
  • Experience with Cadence package design tools is preferred.
  • Knowledge of DoE/DFM/DFR is a plus.
  • Strong communication across design centers to drive projects from design start to sign-off.

Responsibilities

  • Use Cadence tools for design, modeling and simulations.
  • Define package requirements and negotiate with chip/system teams.
  • Conduct routing, stack-up and component placement studies.
  • Collaborate with PCB Layout Engineers to optimize ballmap and die size.
  • Develop multi-signal package models over 50 GHz bandwidth and test structures.
  • Establish performance metrics for organic package technologies.
  • Perform Power Integrity analysis and generate PDN requirements.
  • Develop scripts for checking package parameters and maintaining electrical design guidelines.

Skills

Power integrity analysis
High-speed signaling
Cross-team collaboration

Education

Bachelor’s or Master’s degree in Engineering

Tools

Cadence
Ansys
AutoCAD

Job description

Advanced Micro Devices in San Jose, CA is seeking an experienced package design engineer within the AMD Adaptive and Embedded Computing Group. You will work across chip, technology and systems teams to define cost-effective, high-performance packaging solutions and support from design start to sign-off.

The ideal candidate has hands-on Cadence packaging experience, strong understanding of high-speed signaling and power integrity, and the ability to collaborate across design centers to deliver

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