Packaging Design Engineer for High-Speed FPGA Packages

AMD; San Jose (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.

This is a high visibility role focused on multiple FPGA device package families. The ideal candidate will translate electrical requirements into manufacturable package technologies and collaborate with design centers to drive

Qualifications

• This is a high visibility position working on multiple package families for the FPGA devices.
• The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable.
• This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages.

Responsibilities

• Use Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off.
• Use analytical and simulation tools to define package/module design requirements (technology, stack-up, etc.) in the project conception stages and negotiate with chip/system teams on product specification.
• Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stack-up, manufacturing time etc.) for various device packaging.
• Collaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size.
• Develop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation.
• Come up with performance metrics for organic package technologies in order to design high speed chips and systems.
• Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation.
• Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.

Skills

Cadence tools

Package design

SerDes design

Power Integrity

Modeling & simulation

Education

Bachelor’s or Master’s degree in Engineering

Tools

Cadence

Ansys

AutoCAD

Job description

The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.

This is a high visibility role focused on multiple FPGA device package families. The ideal candidate will translate electrical requirements into manufacturable package technologies and collaborate with design centers to drive