Overlay Development Engineer, Advanced Lithography & DOE

Intel Corporation; Hillsboro (OR); Hybrid; USD 156,000 - 255,000; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Hybrid work model

Job summary

Intel Corporation’s Logic Technology Development team seeks a seasoned Module Development Engineer to lead scientific research enabling advanced device architectures. You will design experiments, analyze results, and collaborate across teams to transfer technology into manufacturing.

You will work with ASML EUV/DUV systems, develop process overlays, and drive DOE/SPC methods to optimize lithography performance in cutting-edge nodes. Hybrid work model offered.

Qualifications

• Bachelor’s degree in a STEM field and extensive hands-on experience in lithography.
• DOE, SPC, and data analysis experience or training.
• Strong communication and cross-functional collaboration skills.

Responsibilities

• Lead scientific research enabling manufacturing of innovative device architectures.
• Design, execute, and analyze experiments to meet engineering specifications.
• Develop and protect intellectual property related to lithography processes.
• Integrate steps for manufacture of complex microprocessors and ramp to volume production.

Skills

Strong communication

Cross-functional teamwork

Attention to detail

Design of Experiments

Statistical Process Control

Troubleshooting

Education

Bachelor’s degree in Materials Science, Chemical Engineering, Chemistry, Physics, Mechanical Engineering, Electrical Engineering, or related STEM

Master’s degree in the same fields

Ph.D. in the same fields

Tools

ASML EUV/DUV scanners

Lithography equipment automation

Process control systems

Job description

Intel Corporation’s Logic Technology Development team seeks a seasoned Module Development Engineer to lead scientific research enabling advanced device architectures. You will design experiments, analyze results, and collaborate across teams to transfer technology into manufacturing.

You will work with ASML EUV/DUV systems, develop process overlays, and drive DOE/SPC methods to optimize lithography performance in cutting-edge nodes. Hybrid work model offered.